Charge Pump Control Circuit Dynamic Frequency Adjustment

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Solution Overview

Problem

Traditional charge pump circuits suffer from inefficiency and increased ripple size due to fixed clock frequencies, leading to unnecessary power consumption and interference, especially when load currents vary over time.

Innovation Solution

A charge pump control circuit with a detecting and controlling circuit that adjusts the clock frequency based on load status, using either voltage or current signals to optimize clock signals and reduce ripple size through feedback control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed high frequency clock is used to maintain voltage on load capacitance, then the voltage stability is improved, but the power consumption increases and efficiency decreases

Engineering Contradiction:
Improvevoltage stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by transitioning from a fixed-frequency clock to a variable-frequency clock that adapts to load conditions. The control circuit dynamically adjusts the clock frequency based on detected load status, using higher frequencies when load demand is high and lower frequencies when demand is low, thereby maintaining voltage stability while optimizing power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of clock frequency from a fixed value to a variable value that can be adjusted according to load requirements. The control circuit modifies the frequency parameter in real-time based on load status detection, allowing the system to achieve both voltage stability and energy efficiency by matching the clock frequency to actual operational needs.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a fixed high frequency clock is used to maintain voltage on load capacitance, then the voltage stability is improved, but the efficiency decreases

Engineering Contradiction:
Improvevoltage stabilityVSAvoidefficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically adjusts clock frequency based on actual load conditions rather than operating at a fixed high frequency. This dynamic adaptation improves efficiency by reducing unnecessary high-frequency operation during low-load conditions while maintaining voltage stability when needed, thereby optimizing the ratio of useful output to total input.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The clock frequency parameter is changed from a static high value to a dynamic value that varies with load status. This parameter change enables the system to maintain voltage stability during high-demand periods while operating at lower frequencies during low-demand periods, thus improving overall operational efficiency.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If a high frequency clock is used to reduce ripple size, then the output voltage quality is improved, but the power consumption increases

Engineering Contradiction:
Improveoutput voltage qualityVSAvoidpower consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The patent uses dynamic frequency adjustment to reduce ripple only when necessary. The control circuit detects load status and increases clock frequency specifically during conditions that generate excessive ripple, rather than maintaining high frequency continuously. This dynamic approach reduces ripple size to improve output voltage quality while minimizing the associated power consumption increase.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The clock frequency parameter is adjusted based on ripple conditions and load status. When ripple becomes excessive, the frequency is increased to reduce it; when ripple is acceptable, the frequency is reduced to save power. This conditional parameter change achieves output voltage quality improvement without sustained high power consumption.

Inventive Principle:
Principle #35Parameter changes

4Power

If the clock frequency is increased to meet high load demand, then the power supply capability is improved, but the ripple amplitude increases

Engineering Contradiction:
Improvepower supply capabilityVSAvoidripple amplitude
Core Design Contradiction:
PowerVSObject-generated harmful factors

Solution Approach 1:

The patent implements feedback control where the control circuit continuously detects load status and adjusts clock frequency accordingly. When load demand increases, the frequency is increased to improve power supply capability; when demand decreases, the frequency is reduced to minimize ripple amplitude. This feedback mechanism coordinates power supply capability and ripple control based on actual operational conditions.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically balances power supply capability and ripple amplitude by adjusting clock frequency in real-time. During high-load periods, high frequency provides sufficient power supply capability; during low-load periods, low frequency minimizes ripple. This dynamic adjustment resolves the contradiction between these two parameters under varying load conditions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7486128B2Charge pump control circuit and control method thereof
Publication Date: 2009.02.03 NOVATEK MICROELECTRONICS CORP
  • US7486128B2 patent drawing
  • US7486128B2 patent drawing
  • US7486128B2 patent drawing

AI summary

A charge pump control circuit and a control method for controlling charge pumps are disclosed. The output terminal of the charge pump is coupled to a load circuit. The charge pump control circuit includes a detecting and controlling circuit and a controlled oscillator. The detecting and controlling circuit is used to detect the load status of the load circuit and output a control signal according to the load status. The controlled oscillator receives the control signal and outputs at least one clock signal. According to the control signal to control a frequency of the clock signal, the charge pump control circuit controls the charge pump.