Charge Pump Circuit with Equalization Units for Fast Start-up
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Solution Overview
Problem
Conventional charge pump circuits face challenges in achieving fast start-up times and high driving capability, which are essential for high-speed operation and efficient power management in semiconductor memories, while also dealing with limitations in capacitor sizes and complexity in timing control.
Innovation Solution
The proposed charge pump circuit incorporates equalization units and capacitors configured to enable or disable equalization units based on clock signals, allowing for efficient charge equalization and faster voltage pumping, utilizing NMOS or PMOS transistors to enhance driving capability and reduce start-up time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional charge pump circuits are used, then voltage pumping function is achieved, but start-up time is slow
Solution Approach 1:
The patent applies preliminary action by pre-charging capacitors before the main charge pumping operation. The circuit includes pre-charge paths that activate before the main pumping phase, ensuring capacitors are ready to transfer charge immediately when needed, thereby reducing start-up time and enabling faster voltage pumping.
Solution Approach 2:
The charge pump circuit is segmented into multiple independent pumping stages with separate control. Each stage can operate semi-independently, allowing the circuit to begin pumping voltage at multiple points simultaneously rather than sequentially, which accelerates the overall voltage pumping speed while maintaining the required function.
2Area of stationary object
If capacitor sizes are reduced, then device area is reduced, but charge pumping performance deteriorates
Solution Approach 1:
The patent applies local quality by optimizing capacitor placement and sizing at specific locations within the circuit. Different capacitors are strategically positioned and sized according to their specific functional requirements in the charge pumping process, allowing small overall device area while maintaining high charge pumping performance at critical nodes.
Solution Approach 2:
The circuit employs nested capacitor structures where capacitors are arranged in series-parallel configurations that maximize voltage pumping efficiency within minimal area. The nested arrangement allows smaller individual capacitors to work together to achieve the same or better performance than a single large capacitor would provide.
3Loss of energy
If charge transfer transistors are added in parallel with diodes, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements periodic action by using clocked control signals to alternately activate diodes and charge transfer transistors in different phases. During certain clock phases, diodes conduct while transistors are off; during other phases, transistors conduct while diodes are off. This periodic switching improves power efficiency by reducing leakage and enabling better charge transfer control, while the regular periodic pattern keeps the control logic relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a charge pump circuit with faster start-up times and higher driving capability, reducing power consumption and making it suitable for high-speed operations while maintaining efficient voltage generation.
Implementation Method 1
The first equalization unit is used for equalizing the charges of the input and the output of the first equalization unit
Implementation Method 2
One end of the second capacitor is coupled to the control end of the first equalization unit
Data Source
AI summary
A charge pump cell with an input and output nodes includes a first, second, and third equalization units, and a first, second, and third capacitors. The input node is coupled to the inputs of the first, second and third equalization units, and the output node is coupled to the second equalization unit. One end of the second capacitor is coupled to the control end of the first equalization unit for enabling or disabling the first equalization unit, and also coupled to the output of the third equalization unit. One end of the third capacitor is coupled to the output of the second equalization unit. One end of the first capacitor is coupled to the control ends of the second and third equalization units, and also coupled to the output of the first equalization unit.