Charge Pump Latch-Up Prevention via Equipotential Well Coupling
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Solution Overview
Problem
Semiconductor charge pump cells are prone to internal latch-up, particularly during initial cycles of the clock signal, due to parasitic pnp and npn structures, which inhibits normal operation and increases power consumption, especially in portable battery applications.
Innovation Solution
Coupling the n-well and p-well regions to a common local potential, effectively shorting the parasitic pnp and npn structures to prevent forward biasing and latch-up, by ensuring both regions operate at a common local minimum potential, thereby disabling the parasitic transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If charge pump cells are operated at high power supply voltages, then voltage level shifting capability is improved, but internal latch-up occurs due to forward biasing of parasitic pnp and npn structures
Solution Approach 1:
The patent applies equipotentiality by coupling the n-well and p-well regions to a common local potential (V LOW ), creating an equipotential environment that prevents voltage differences between these regions. This eliminates the forward biasing condition of parasitic pnp and npn structures, allowing the charge pump to operate at high voltages without latch-up. The common potential coupling ensures that both wells remain at the same electrical potential, preventing harmful current flow through parasitic paths.
2Temperature
If charge pump cells are operated at high temperatures, then operating range is extended, but internal latch-up is exacerbated due to increased parasitic activity
Solution Approach 1:
The equipotentiality principle addresses temperature-related latch-up by maintaining common potential coupling between n-well and p-well regions. At elevated temperatures, parasitic structures become more active, but the equipotential connection ensures no voltage differential exists to drive latch-up currents. This approach allows extended temperature operation without compromising reliability.
3Device complexity
If conventional charge pump structures are used, then device complexity is minimized, but power consumption increases due to latch-up events
Solution Approach 1:
The patent maintains minimal device complexity by implementing equipotentiality through simple potential coupling connections rather than complex active control circuits. The n-well and p-well regions are coupled to V LOW through straightforward electrical connections, avoiding the need for additional transistors, sensors, or control logic. This simple equipotential approach prevents latch-up and reduces power consumption without significantly increasing device complexity.
4Ease of manufacture
If n-well and p-well regions are left floating, then manufacturing process is simplified, but parasitic pnp and npn structures become forward biased
Solution Approach 1:
The patent resolves the manufacturing simplicity versus parasitic activation contradiction by implementing equipotentiality through potential coupling. Instead of leaving wells floating or using complex isolation structures, the invention couples n-well and p-well to a common potential (V LOW ), which is a simple manufacturing step. This equipotential connection prevents parasitic transistor activation while maintaining ease of manufacture, as it requires only standard doping and connection processes.
Data Source
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AI summary
A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions disposed in the first well region. A second well region is formed in the substrate. A third well region is formed within the second well region. A second transistor includes first and second conduction regions disposed in the third well region. The second well region and third well region are coupled to a common terminal. The common terminal receives a local potential and the first well region and second well region are commonly maintained at the local potential. The first transistor and second transistor operate within the charge pump cell. A plurality of charge pump cells can be cascaded together with an output of a first charge pump cell coupled to an input of a second charge pump cell.