Charge Pump FET Layout Matching for PLL Mistracking
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Solution Overview
Problem
In 7 nm semiconductor technology, device tracking parameters often fall outside specified distributions, leading to mistracking issues in FETs, particularly affecting PLL circuits due to anomalies in threshold voltages and layout dependencies, resulting in chip failures.
Innovation Solution
The solution involves improving tracking between FETs by ensuring identical FEOL shapes and arrangements for charge pump slices and current reference circuits, with specific BEOL interconnect patterns and shielding to mitigate mistracking, and using a 'daisy chain' configuration for buffer signals to maintain pulse widths and control currents effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If FETs are physically distanced on semiconductor chip, then manufacturing variability is reduced, but tracking between FETs deteriorates
Solution Approach 1:
The patent segments the FET layout into identical FEOL shapes for both the charge pump circuit and current reference circuit, creating modular units that can be replicated. This segmentation allows each FET to have consistent manufacturing parameters while maintaining physical proximity for tracking, resolving the contradiction between manufacturing precision and device tracking.
Solution Approach 2:
The patent applies local quality by ensuring that the FEOL shapes and arrangements are locally identical for matching FETs, while allowing BEOL interconnect patterns to differ for functional differentiation. This localized consistency in critical manufacturing regions improves tracking without compromising manufacturing precision.
2Reliability
If FEOL shapes and arrangements are made identical for charge pump and current reference circuits, then FET tracking improves, but circuit functionality may be compromised
Solution Approach 1:
The patent merges the FEOL fabrication characteristics of the charge pump circuit and current reference circuit by making their shapes and arrangements identical. This merging ensures that FETs in both circuits experience the same manufacturing conditions, improving tracking while functional differentiation is achieved through BEOL interconnect patterns.
Solution Approach 2:
The patent resolves the contradiction by moving the differentiation function to another dimension - from FEOL shapes to BEOL interconnect patterns. The FEOL layer maintains identical shapes for tracking, while the BEOL layer provides functional differentiation through different interconnect arrangements, effectively using vertical layering to solve the contradiction.
3Adaptability or versatility
If BEOL interconnect patterns are modified for current reference circuit, then circuit functionality is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interconnect design into FEOL and BEOL layers, assigning different complexity levels to each. The FEOL layer maintains simple, identical shapes for manufacturing ease, while the BEOL layer handles the complex interconnect patterns needed for functional differentiation, distributing complexity across layers to reduce overall manufacturing burden.
Data Source
AI summary
A phase locked loop having a charge pump is described. The charge pump relies on close matching of FETs (Field Effect Transistor) electrical parameters to FETs in a current reference circuit. To achieve close matching of FET electrical performance, FEOL (Front End Of Line), comprising all FET shapes, of the current pump is identical in shapes and layout to the current reference circuit. BEOL (Back End Of Line) differs between the charge pump and the current reference circuit. The charge pump and the current reference circuit are arranged in a row. A shield circuit having FEOL shapes and layout identical to the current pump may be placed at each end of the row.