Charge Pump Circuit for Monolithic Flash Memory Voltage Generation
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Solution Overview
Problem
The existing charge pump circuits in semiconductor memory devices, such as MONOS flash memories, require multiple circuits to generate different voltages for writing operations, leading to increased chip size and cost, especially in devices with small memory capacity, as they struggle to simultaneously generate high voltages with sufficient current drivability for both the control gate and drain.
Innovation Solution
A semiconductor memory device with a charge pump circuit that includes a first pump block for generating a high voltage and a second pump block for generating a lower voltage, both capable of outputting distinct voltage magnitudes, allowing for efficient voltage supply to both the control gate and drain using a single charge pump circuit, thereby reducing the overall circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple charge pump circuits are used to generate different voltages for control gate and drain, then the voltage generation capability is sufficient, but the chip size increases
Solution Approach 1:
The charge pump circuit is designed to perform multiple functions by generating different voltage levels (first voltage and second voltage) through a single unified circuit structure. The pump blocks can operate in different configurations to provide appropriate voltages for both the control gate and drain, eliminating the need for separate charge pump circuits and thereby reducing chip size while maintaining full voltage generation capability
Solution Approach 2:
The charge pump circuit is divided into multiple pump blocks that can be selectively activated or configured based on the required voltage output. This segmentation allows the single circuit to generate different voltage levels by engaging specific pump blocks, enabling versatile voltage generation without requiring multiple complete charge pump circuits
2Area of stationary object
If a single charge pump circuit generates both high and lower voltages, then the chip size is reduced, but the current drivability for high voltage generation becomes insufficient
Solution Approach 1:
The charge pump circuit employs dynamic switching mechanisms that allow it to adapt its configuration based on the required voltage and current demands. When high voltage is needed, the circuit can switch to a configuration optimized for voltage multiplication; when lower voltage with higher current is needed, it can reconfigure to provide sufficient current drivability, thus meeting both requirements within a single compact circuit
3Reliability
If multiple charge pump circuits are used, then the voltage generation reliability is sufficient, but the device complexity increases
Solution Approach 1:
By designing a single charge pump circuit capable of generating multiple voltage levels through different operating modes, the invention reduces the number of separate circuits needed. This universal design maintains voltage generation reliability by ensuring that all required voltages can be produced by one well-tested circuit architecture, thereby reducing overall device complexity while preserving functional reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient driving of multiple nodes with different current supply capacities using a single charge pump circuit, reducing chip size and cost while maintaining the necessary voltage levels for effective writing operations.
Implementation Method 1
a charge pump circuit for generating a first voltage higher than a supply voltage and a second voltage lower than the first voltage
Data Source
AI summary
A semiconductor memory device includes: a memory cell array including a plurality of memory cells arranged in rows and columns for holding information, each of the memory cells having a control gate; a plurality of word lines extending in a row direction, each of the word lines being connected to the control gates of the memory cells of a corresponding row of the memory cell array; a plurality of bit lines extending in a column direction and connected to sources or drains of the memory cells; a row decoder for selecting any of the plurality of word lines; a column decoder for selecting any of the plurality of bit lines; a charge pump circuit for generating a voltage higher than a supply voltage; and a first switch located in a connection path between the row decoder and the charge pump circuit.