Multi-Stage Charge Pump Architecture for Flash Memory Voltage Generation
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Solution Overview
Problem
Conventional charge pump circuits require significant silicon area and complexity to generate multiple high voltage levels, as they often necessitate replicating charge pumps or linear regulators for each voltage level, leading to inefficiencies and increased die area.
Innovation Solution
A charge pump architecture with multiple pump stages and output voltage levels, where each output voltage is independently regulated using pulse-skip or linear regulation methods, and can be controlled by a single set of clock signals, allowing for multiple output voltages to be generated within a single charge pump circuit without replicating regulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple charge pumps or linear regulators are replicated for each voltage level, then multiple high voltage levels can be generated, but silicon area and circuit complexity increase significantly
Solution Approach 1:
The patent combines multiple charge pump stages (first group with m stages, second group with n-m stages) into a single integrated circuit that can generate multiple voltage levels (V1, V2, etc.) simultaneously. This merging approach eliminates the need for separate replicated charge pumps for each voltage level, thereby reducing silicon area while maintaining the capability to provide multiple high voltage levels for different flash memory operations
Solution Approach 2:
The charge pump circuit is designed as a universal multi-functional device that can generate multiple different voltage levels (V1 for program operation, V2 for erase operation, etc.) from a single power supply VDD. This multi-functionality allows the same circuit structure to serve multiple voltage generation needs without requiring separate dedicated circuits for each voltage level
2Adaptability or versatility
If multiple charge pumps or linear regulators are replicated for each voltage level, then multiple high voltage levels can be generated, but circuit complexity increases
Solution Approach 1:
The patent merges multiple charge pump stages into a single coordinated circuit structure where the first group of m stages and the second group of n-m stages work together to generate multiple voltage levels. This unified structure reduces circuit complexity compared to having separate replicated charge pumps, as the stages share common control signals and are integrated into a single operational framework
Solution Approach 2:
The charge pump circuit is segmented into functional groups (first group with m stages, second group with n-m stages) that can be independently controlled through pulse-skip regulation. This segmentation allows complex voltage generation to be broken down into manageable stages that can be regulated independently, reducing overall circuit complexity while maintaining multiple output capabilities
3Reliability
If pulse-skip regulation is used to control output voltage, then voltage regulation is achieved, but pump clocks are suppressed when output voltage exceeds maximum value
Solution Approach 1:
The patent implements pulse-skip regulation using feedback comparators that continuously monitor the output voltage levels. When the output voltage exceeds the maximum required value, the comparator triggers suppression of the pump clock signal, stopping the charge pumping action. When the voltage drops below the threshold, the clock is re-enabled to resume charging. This feedback mechanism ensures reliable voltage regulation while minimizing unnecessary charge pumping activity
4Area of stationary object
If all n-channel transistors are used in flash memory drivers, then memory performance and silicon area are improved, but voltage loss equal to threshold voltage occurs
Solution Approach 1:
The patent generates multiple different voltage levels (V1, V2, etc.) using the charge pump circuit to compensate for the threshold voltage loss inherent in all-nchannel transistor drivers. By providing elevated voltage levels through the charge pump, the system maintains adequate voltage headroom for proper driver operation while continuing to use the area-efficient all-nchannel transistor architecture in the flash memory array
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces silicon area usage and complexity by enabling multiple output voltages within a single charge pump, allowing for efficient generation and regulation of high voltage levels without the need for redundant regulator circuits, thus improving efficiency and reducing die area.
Implementation Method 1
Charge pumps are switched-capacitor circuits employed to obtain either an output voltage higher than that of the power supply (VDD) or a negative voltage in an electronic system. Each pumping stage includes capacitors, switches and drivers and is controlled by one or more clock signals. Voltage multiplication is obtained by properly charging and switching the pumping stage capacitors.
Data Source
AI summary
A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.