Four-Phase Charge Pump Timing to Cut Ground Bounce Noise
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Solution Overview
Problem
Charge pumps used in embedded non-volatile memories face inefficiencies due to voltage gain degradation from threshold voltage (Vth) issues and high power consumption, leading to significant ground bounce and simultaneous switching noise, especially in four-phase clock schemes, which limit output current and voltage efficiency.
Innovation Solution
A charge pump system incorporating a four-phase clock generator with serially connected delay circuits and two charge pump circuits, where the first and second charge pump circuits receive staggered signal groups to optimize overlapping times and reduce peak current, thereby alleviating ground bounce and improving output current and voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a four-phase clock scheme is used to increase voltage gain, then the voltage gain degradation due to Vth can be alleviated, but the simultaneous switching noise and ground bounce increase significantly
Solution Approach 1:
The clock signal distribution is segmented into multiple phases with different timing, so that not all clock switches switch simultaneously. This divides the switching events across time, reducing peak current and noise while maintaining the voltage gain benefits of the four-phase scheme.
Solution Approach 2:
The patent employs periodic clock signals with specific phase shifts to control the switching sequence. By using periodic actions with optimized timing, the system achieves continuous voltage pumping while distributing switching noise over time, preventing simultaneous switching peaks.
2Strength
If clock switches switch simultaneously on the clock edge to drive the charge pump, then the voltage gain is maximized, but the DC short current and power consumption increase
Solution Approach 1:
The patent introduces preliminary timing adjustments to clock signals, preparing the switching sequence in advance to avoid simultaneous switching. This preliminary action optimizes the timing of each clock phase to reduce overlapping current peaks while maintaining effective voltage pumping.
Solution Approach 2:
The clock timing parameters are dynamically optimized to balance voltage gain and power consumption. By making the timing relationships adjustable and optimized rather than fixed, the system can reduce DC short current while maintaining the necessary voltage gain for operation.
3Strength
If the number of stages in the charge pump is increased to achieve higher output voltage, then the output voltage increases, but the voltage gain decreases due to body effect
Solution Approach 1:
The patent ensures continuous and optimized charge transfer across multiple stages by maintaining proper timing overlap between phases. This continuity compensates for the cumulative body effect in multi-stage configurations, maintaining effective voltage gain even as output voltage increases with additional stages.
Solution Approach 2:
The patent optimizes timing parameters and voltage levels across different stages to compensate for body effect. By adjusting clock phase relationships and voltage timing, the system maintains voltage gain efficiency even when scaling to higher output voltages through multiple stages.
Data Source
AI summary
The present invention discloses a charge pump system with low noise and high output current and voltage, comprising: a four phase clock generator used to generate a first signals group; a serial of delay circuits coupled to said four phase clock generator, wherein each of said delay circuits is coupled to a previous delay circuit relative to each of said delay circuits for delaying a signals group received from said previous delay circuit; a first charge pump circuit coupled to the four phase clock generator and the delay circuits; and an output terminal coupled to the first charge pump circuit; wherein high level of said first signal overlaps two sections of high level of said third signal to generate a first overlapping time and a second overlapping time, and said first overlapping time is not equal to said second overlapping time.