Charge Pump Input Buffer Clock Frequency Decoupling
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Solution Overview
Problem
Existing power supply circuits in integrated circuits require an external negative bias voltage to drive the negative rail of analog-to-digital converters, increasing system cost and complexity, especially when digitizing signals at ground or below ground.
Innovation Solution
An integrated circuit with a charge pump circuit that generates a negative power supply voltage using a clock signal with a frequency different from the ADC's clock signal, reducing noise interference by selecting frequencies that align with the rejection band of the ADC's digital filter, and utilizing a clock divider to generate both clock signals from an oscillator frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an external negative power supply voltage is provided to drive the negative rail of the input buffer, then the A/D converter can digitize signals at ground or below ground, but the system cost and complexity increase
Solution Approach 1:
The patent combines the negative power supply generation function within the integrated circuit itself by using a charge pump circuit that generates the negative voltage from the positive supply voltage. This eliminates the need for an external negative power supply and reduces system complexity while maintaining the ability to digitize signals at ground or below ground.
Solution Approach 2:
The integrated circuit generates its own negative power supply voltage using an on-chip charge pump circuit that converts the positive supply voltage to the required negative voltage. This self-service approach eliminates external components and reduces system complexity while enabling signal digitization at ground or below ground levels.
2Device complexity
If a charge pump circuit is used to generate negative power supply voltage on-chip, then system complexity is reduced, but noise is introduced into the ADC
Solution Approach 1:
The patent uses periodic clock signals to drive the charge pump circuit at specific frequencies that are intentionally chosen to place the noise generated by the charge pump into frequency ranges where the A/D converter has reduced sensitivity. This periodic action with carefully selected frequencies minimizes the impact of noise on conversion accuracy.
Solution Approach 2:
The patent converts the harmful noise generated by the charge pump into a beneficial situation by selecting clock frequencies that place the noise in rejection bands of the A/D converter's digital filter. The noise that would normally degrade performance is instead positioned where it is naturally attenuated, turning a harmful effect into a non-problematic one.
3Object-generated harmful factors
If the charge pump clock frequency is different from the ADC clock frequency, then noise in the frequency range of interest is reduced, but timing synchronization becomes more complex
Solution Approach 1:
The patent introduces a clock divider circuit as an intermediary component that takes a master clock signal and divides it to generate both the ADC clock signal and the charge pump clock signal. This intermediary ensures that both clocks are derived from the same source, maintaining synchronization while allowing different frequencies, and simplifies the overall timing architecture.
Solution Approach 2:
The patent uses a single master clock signal that serves multiple functions by being divided to generate both the ADC clock and the charge pump clock. This multi-functional approach simplifies the clocking architecture while enabling different operating frequencies for the ADC and charge pump, thereby reducing noise in the frequency range of interest.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the digitization of signals at ground or below ground without an external negative power supply, reducing noise interference and system complexity while maintaining accurate conversion times.
Implementation Method 1
a charge pump circuit providing a negative power supply voltage to the integrated circuit
Data Source
AI summary
An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal.