Charge Pump Leakage Compensation for Low-Jitter PLLs
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Solution Overview
Problem
Charge leakage in charge pump circuits of phase lock loops introduces errors in phase detection, leading to clock jitter in the output clock due to the use of leaky MOS transistors in deep submicron CMOS integrated circuits.
Innovation Solution
A charge pump circuit with a capacitive load shunt, a current sensor, and a feedback network that adjusts a bias voltage to compensate for leakage current, ensuring zero net current when the phase signal is inactive, thereby reducing clock jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MOS transistors are used in charge pump circuit for phase lock loop, then the circuit can be implemented in CMOS integrated circuit, but charge leakage occurs due to short channel effects in deep submicron processes
Solution Approach 1:
A current sensor is introduced as an intermediary component to detect the leakage current in the charge pump circuit. The sensor monitors the current flowing through the MOS transistors and provides feedback information about the leakage magnitude, enabling the system to compensate for the charge leakage while maintaining CMOS integration benefits
Solution Approach 2:
A feedback network is implemented that uses the current sensor output to dynamically adjust the charge pump operation. The feedback mechanism detects leakage current and automatically compensates by adjusting the control signals to the charge pump, thereby maintaining phase detection accuracy despite charge leakage in deep submicron CMOS transistors
2Speed
If charge pump circuit operates with leaky MOS transistors, then high-speed operation is achieved, but clock jitter increases due to charge leakage errors
Solution Approach 1:
The patent replaces the traditional voltage-mode phase detection mechanism with a current-mode detection system that directly measures the actual current flowing through the charge pump. This substitution allows the system to detect and compensate for charge leakage effects in real-time, maintaining phase detection accuracy even during high-speed operation where leakage is more significant
3Volume of moving object
If deep submicron CMOS process is used, then device size is reduced and integration is improved, but charge leakage increases due to short channel effects
Solution Approach 1:
The charge pump circuit is designed to self-diagnose and self-compensate for its own charge leakage problems. The current sensor continuously monitors the actual current flow, and the feedback network automatically adjusts the pump operation to compensate for leakage losses, allowing the miniaturized deep submicron devices to maintain performance without requiring larger compensation circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces clock jitter by accurately compensating for leakage currents, stabilizing the output voltage and frequency of the phase lock loop, ensuring precise phase locking.
Implementation Method 1
a current sensor inserted between the internal node and the output node for sensing the current
Implementation Method 2
a feedback network for adjusting the bias voltage in accordance with an output of the current sensor when the phase signal is in an inactive state
Implementation Method 3
The filter serves as a capacitive load for the charge pump circuit, and effectively filters and converts the current-mode detector output signal into a voltage-mode control signal
Data Source
AI summary
An apparatus is disclosed, the apparatus comprising: a charge pump for receiving a phase signal representing a result of a phase detection and for outputting a current flowing between an internal node and an output node; a capacitive load shunt at the output node; a current source controlled by a bias voltage for outputting a compensation current to the internal node; a current sensor inserted between the internal node and the output node for sensing the current; and a feedback network for adjusting the bias voltage in accordance with an output of the current sensor.