Charge Pump Level Translator for High-Speed Memory Drivers
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Solution Overview
Problem
Existing interface circuits between microprocessors and DDR SDRAM memory devices face challenges in coherent communication due to differing power supply voltages, leading to inefficiencies in memory access speed and switching speed, particularly when the microprocessor core voltage is lower than the memory supply voltage.
Innovation Solution
The implementation of a level translator circuit with a charge pump to improve switching speed and mitigate current-sourcing-current-sinking contention, using a PMOS cross quad and NMOS transistors to generate a differential output signal, and programmable configuration to adapt to different memory supply voltages through the use of charge pumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a standard level shifter circuit is used to translate voltages between microprocessor and memory device, then voltage level translation is achieved, but switching speed becomes insufficient for high-speed memory operations
Solution Approach 1:
The patent applies dynamics by making the level shifter circuit configurable and adaptable to different voltage conditions. The circuit can be programmed to select between different operating modes (e.g., charge pump enabled/disabled, different PMOS/NMOS configurations) depending on the specific voltage requirements of the memory device, allowing optimal performance across varying conditions rather than being fixed for a single operation
Solution Approach 2:
The patent changes physical parameters by introducing a charge pump mechanism that actively modifies voltage levels during operation. The charge pump generates elevated voltage levels (e.g., VDDQ + VDD) to ensure proper switching of PMOS transistors during level translation, directly addressing the switching speed limitation by providing enhanced voltage drive capability when needed
2Use of energy by moving object
If the microprocessor core voltage is lowered to reduce power consumption, then power efficiency improves, but the ability to drive memory devices with higher supply voltages deteriorates
Solution Approach 1:
The patent introduces an intermediary voltage boosting mechanism (charge pump) between the low-voltage microprocessor core and the high-voltage memory interface. This intermediary allows the core to operate at low voltage for power efficiency while the charge pump mediates the voltage translation to appropriate levels for driving memory devices, decoupling the core voltage from the I/O voltage requirements
Solution Approach 2:
The level shifter circuit is designed to be dynamically configurable, allowing it to adapt its operating mode based on the specific memory device voltage requirements. This programmability enables the same circuit to work with different memory types (e.g., DDR3, DDR4, LPDDR) that have different supply voltages, maintaining voltage compatibility across various scenarios
3Speed
If charge pump is used to boost voltage for faster switching, then switching speed improves, but current-sourcing-current-sinking contention increases
Solution Approach 1:
The patent applies dynamics by making the charge pump operation configurable rather than always active. The circuit can be programmed to enable or disable the charge pump based on the specific operating conditions and memory device requirements, allowing optimal balance between switching speed and power consumption for each scenario
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances memory access speed and switching efficiency by resolving voltage translation issues, allowing the microprocessor to effectively drive DDR memory devices with varying supply voltages, thereby improving overall system performance.
Implementation Method 1
charge pump circuitry to a gate of a PMOS FET inside the PMOS cross quad
Data Source
AI summary
Embodiments relate to circuits, electronic design assistance (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on different supply voltages. In one embodiment, a programmable level translator device is implemented using an NMOS transistor pair and a PMOS cross quad. The switching characteristics are modified with the use of a charge pump connected to the gate terminals of two of the PMOS transistors within the PMOS cross quad. Transmission gates are also employed to engage and disengage the charge pump based on a control switch. In various embodiments, the level translator device works with a number of memory devices operating over a wide range of power supply voltages.