Charge Pump Circuit for Low Input Voltage Operation

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Solution Overview

Problem

Conventional charge pump circuits using voltage doubler circuits face limitations in drive capability due to the absolute gate-source voltage required to turn on transistors, which restricts the minimum input voltage at which the circuit can operate and affects the ability to deliver load current.

Innovation Solution

The proposed charge pump circuit design includes a series of voltage doubler circuits where the gates of NMOST switches are driven by higher voltage doubler circuits, and PMOS switches are driven by lower voltage doubler circuits, allowing for a higher gate-source voltage for transistor switching, reducing on-resistance and enabling operation at lower input voltages or increased load current delivery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If conventional voltage doubler circuits are used with absolute gate-source voltage switching, then the circuit structure is simple, but the drive capability is limited and minimum input voltage is restricted

Engineering Contradiction:
Improvedrive capabilityVSAvoidcircuit structure
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The charge pump circuit is divided into multiple voltage doubler circuits connected in series, where each stage independently doubles the voltage. This segmentation allows each transistor to operate with sufficient gate-source voltage while the overall circuit achieves high voltage multiplication, resolving the contradiction between drive capability and circuit structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from single-stage voltage multiplication to multi-stage cascaded architecture, adding the dimension of stage number to the system. This allows the circuit to overcome the gate-source voltage limitation of individual transistors by distributing the voltage multiplication across multiple stages, thereby improving drive capability without excessive complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Power

If higher gate-source voltage is applied to transistors, then on-resistance decreases and load current capability increases, but input voltage requirement increases

Engineering Contradiction:
Improveload current deliveryVSAvoidinput voltage requirement
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

Each voltage doubler stage preliminarily doubles the input voltage before passing it to the next stage. This preliminary action at each stage ensures that transistors in subsequent stages receive sufficient gate-source voltage to achieve low on-resistance and high load current capability, while the overall circuit can operate from low input voltage.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediate voltage doubling stages as mediators between the low input voltage source and the high power output requirement. These intermediate stages progressively build up the voltage, allowing each transistor to operate in its optimal conduction region without requiring high input voltage, thus achieving both low input voltage operation and high load current delivery.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10084375B2Charge pump suitable for low input voltages
Publication Date: 2018.09.25 DIALOG SEMICONDUCTOR BV
  • US10084375B2 patent drawing
  • US10084375B2 patent drawing
  • US10084375B2 patent drawing

AI summary

A charge pump circuit suitable for low input voltages is presented. The charge pump circuit has a first clock signal generator, a second clock signal generator, and n voltage doubler circuits. The voltage doubler has an input, an output, a first capacitor connected to the first clock signal generator, a second capacitor connected to the second clock signal generator, a first NMOST having the source connected to the input and the drain connected to the first capacitor, a second NMOST having the connected to the source of the first NMOST and the drain connected to second capacitor, a first PMOST having the drain connected to the first capacitor and the source connected to the output, a second PMOST having the source connected to the source of the first PMOST and the drain connected to the second capacitor.