High-Voltage Charge Pump Using Low-Voltage Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Charge pump circuits face challenges in implementing high-voltage transfer efficiently due to parasitic p-n junctions and the need for multiple stages, which increases complexity and time for charge transfer.
Innovation Solution
A two-stage charge pump circuit using a power supply of 2*VDD, with diodes D4 and D5 operative during start-up, and transistors rated for operation at less than the supply voltage, reducing the number of stages required and enhancing response time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the number of stages is increased to achieve higher output voltage, then the voltage conversion capability is improved, but the charge transfer time is extended
Solution Approach 1:
The charge pump circuit is divided into multiple stages, each responsible for a portion of the voltage multiplication. By using two stages with 2*VDD power supply, the circuit achieves high voltage output while maintaining reasonable transfer speed, as each stage handles a manageable voltage increment rather than requiring many small stages
Solution Approach 2:
The patent changes the power supply voltage parameter to 2*VDD, which allows each transistor to operate within its rated voltage while achieving higher overall output voltage through the two-stage configuration. This parameter optimization reduces the number of stages needed compared to using VDD power supply
2Strength
If transistors are rated for operation at the full supply voltage, then the voltage handling capability is improved, but the manufacturing complexity and form-factor increase
Solution Approach 1:
The voltage handling requirement is segmented across multiple transistors in series. Each transistor only needs to be rated for a portion of the total supply voltage (e.g., VDD instead of 2*VDD), which simplifies manufacturing and reduces form-factor while the series configuration achieves the required voltage handling capability
Solution Approach 2:
The patent optimizes transistor voltage ratings to match the actual voltage stress they experience in each stage, rather than requiring all transistors to be rated for the maximum supply voltage. This parameter optimization reduces manufacturing complexity and allows smaller device geometries
3Device complexity
If parasitic p-n junctions are present in diodes, then the circuit structure is simplified, but charge leakage occurs reducing transfer efficiency
Solution Approach 1:
The patent introduces an intermediate n-well layer between the p-substrate and the diode structures. This intermediary n-well acts as an isolation barrier that prevents charge leakage through parasitic p-n junctions while maintaining the functional diode structure, thus preserving both circuit simplicity and charge transfer efficiency
Solution Approach 2:
The patent converts the potentially harmful parasitic p-n junction leakage into a beneficial isolation mechanism by using the n-well to create controlled p-n junctions that prevent unwanted charge leakage paths, turning what would be a defect into a protective feature
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the number of stages needed for charge transfer, improves response time, and allows transistors to be manufactured with a smaller form-factor, maintaining reliability and efficiency.
Implementation Method 1
storing the charge in a first capacitor of the first circuit at a first point in time
Implementation Method 2
a first diode, a second diode... transferring the charge stored in the first capacitor to a second capacitor of a second circuit
Implementation Method 3
transistors rated for operation at less than the supply voltage
Data Source
AI summary
Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.