Multi-mode Charge Pump for Transistor Mismatch Immunity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In recent semiconductor processes, especially at 7 nm technology, device parameters such as FET thresholds often exceed specified distributions, leading to anomalies that cause unacceptable failure rates in circuits like phase locked loops (PLLs), with different chips having unique anomalies requiring individualized fixes.
Innovation Solution
A PLL design with a charge pump having multiple modes, where each chip can select a mode based on laboratory measurements to adjust currents and mitigate mistracking issues, using controllable current sources and on-chip storage to ensure yield and stability, and employing a daisy chain of buffers to preserve short pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple selectable modes are implemented in the charge pump to address device anomalies, then yield and reliability are improved, but device complexity increases
Solution Approach 1:
The charge pump implements multiple selectable modes (first mode, second mode, third mode) that dynamically adjust the operation of controllable current sources based on detected device anomalies. The circuit transitions between different operational states to compensate for threshold voltage mismatches and tracking errors in FETs, thereby maintaining PLL stability across varying device conditions.
Solution Approach 2:
The invention changes operational parameters of the charge pump by selecting different modes that adjust current source characteristics. Each mode modifies the current delivery behavior to compensate for specific device anomalies, such as threshold voltage shifts or tracking errors, without requiring physical hardware changes.
2Manufacturing precision
If per-chip mode selection is implemented to address unique anomalies, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The system performs preliminary characterization of device parameters (such as FET threshold voltages) during or after manufacturing, identifies anomalies in each chip, and pre-selects the appropriate operating mode before the chip is deployed. This preliminary action allows each chip to be customized for its specific device characteristics without requiring complex post-manufacturing adjustments.
Solution Approach 2:
Each chip autonomously selects its own operating mode based on its inherent device characteristics and anomalies. The per-chip mode selection mechanism enables the circuit to self-adjust without requiring external intervention or complex manufacturing processes, thereby maintaining ease of manufacture while achieving high precision.
3Reliability
If extensive testing is performed to determine optimal mode selection, then reliability is improved, but loss of time increases
Solution Approach 1:
The testing process implements a priority-based approach where modes are tested in a predetermined order of likelihood to provide yield and stability. Rather than exhaustively testing all possible modes, the system performs partial testing starting with the most promising modes, selecting the first acceptable mode found. This reduces testing time while maintaining high reliability by focusing on the most effective configurations first.
Data Source
AI summary
A phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made for each chip. The selected mode mitigates effects of device mistracking anomalies for each chip. A method is provided to show how the modes are determined and prioritized.