Charge-Pump Current-Mode Neuron for Compute-in-Memory Speed
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Solution Overview
Problem
The Von Neumann architecture in computer processing creates a bottleneck for data flow in machine learning applications, hindering processing speed due to data movement between memory and processing units.
Innovation Solution
Implementing a charge-pumped-based current-mode compute-in-memory bitcell (neuron) that distributes data processing hardware across bitcells, utilizing a filter weight capacitor, switches, and a bias circuit to enhance processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Von Neumann architecture is used for data processing, then data can be stored and processed separately, but data flow becomes a bottleneck for processing speed
Solution Approach 1:
The patent merges memory and processing functions into a single compute-in-memory bitcell. The neuron circuit integrates weight storage (filter weight capacitor), computation (output transistor), and readout (bit line connection) within the same memory cell structure, eliminating the need for separate memory and processing units and thus removing the data flow bottleneck.
Solution Approach 2:
The bitcell is designed to perform multiple functions: storing filter weights in the capacitor, performing multiplication operations through transistor switching, accumulating results in the bit line, and supporting both training and computation phases. This multi-functionality eliminates the need for separate dedicated hardware for each operation.
2Productivity
If multiple bitcells are used to achieve high processing density, then processing capacity increases, but area consumption and device complexity increase
Solution Approach 1:
The patent combines multiple functions (weight storage, computation, readout) into a single bitcell structure, achieving high processing density without proportionally increasing area. The filter weight capacitor shares the bitcell structure with the output transistor and bit line connection, maximizing functional integration within minimal space.
Solution Approach 2:
Each bitcell serves as a universal computing unit that can store weights, perform computations, and output results. This multi-functionality allows high processing density to be achieved with fewer bitcells compared to traditional architectures that require separate dedicated components for each function.
3Productivity
If boosted voltage is applied to the gate of the output transistor, then processing efficiency increases, but voltage control complexity increases
Solution Approach 1:
The patent applies boosted voltage to the output transistor gate during specific operational phases (training and computation) before the actual processing occurs. The voltage boosting is prepared in advance through the charge pump circuit, ensuring optimal transistor performance is established before data processing begins, thereby improving efficiency without requiring complex real-time voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases processing speed and density by reducing the need for multiple bitcells, allowing for efficient training and computation phases with boosted voltages, thus improving machine learning performance.
Implementation Method 1
a charge pump capacitor; a filter weight capacitor
Implementation Method 2
driving a current through a diode-connected transistor to charge a charge pump capacitor to a charge pump voltage
Implementation Method 3
conducting a mirrored version of the current through the output transistor responsive to the charging of the gate of the output transistor
Data Source
AI summary
A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.