Charge-Pump Current-Mode Neuron for Compute-in-Memory Speed
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Solution Overview
Problem
The traditional Von Neumann architecture for machine learning applications is bottlenecked by data flow to and from memory, hindering processing speed, which is addressed by distributing data processing hardware across bitcells in compute-in-memory architectures.
Innovation Solution
A charge-pumped-based current-mode compute-in-memory bitcell (neuron) is introduced, featuring a bias circuit, a bit line, an output transistor, a filter weight capacitor, digital-to-analog converter, and multiple switches, allowing for efficient charging and mirroring of currents during training and computation phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is retrieved from memory to be processed in an arithmetic and logic unit (Von Neumann architecture), then data processing can be performed, but data flow to and from memory becomes a bottleneck for processing speed
Solution Approach 1:
The patent combines memory storage and data processing functions into a single integrated structure. The compute-in-memory bitcell integrates transistor-based logic operations directly within the memory cell, eliminating the need for separate data movement between memory and processing units. This merging of storage and computation functions resolves the bottleneck caused by data flow between separate memory and processing components.
2Productivity
If data processing hardware is distributed across bitcells in compute-in-memory architectures, then processing speed improves, but device complexity increases
Solution Approach 1:
The compute-in-memory bitcell is designed as a universal unit that can perform multiple functions: data storage, arithmetic operations, and logic operations. Each bitcell contains transistors that can function as both memory elements and processing elements, allowing a single structure to handle diverse computational tasks without requiring specialized hardware for each function, thereby managing complexity while maintaining high productivity.
Solution Approach 2:
The patent divides the computing system into discrete, modular bitcell units that can be independently configured and operated. Each bitcell is a self-contained module with its own transistors and storage elements, allowing the system to scale by simply adding more identical modules rather than designing increasingly complex monolithic structures. This segmentation manages device complexity through modularity while enabling high throughput through parallel operation of multiple bitcells.
3Productivity
If multiple SRAM bitcells are used to implement neurons, then processing capability increases, but semiconductor area increases
Solution Approach 1:
The patent merges the functions of multiple SRAM bitcells into a single compute-in-memory bitcell structure. By integrating storage and processing functions that would otherwise require separate SRAM cells into one unified structure, the design achieves the same neuron processing capability with reduced semiconductor area. The integrated bitcell eliminates redundant components and interconnect structures that would be present if multiple separate SRAM bitcells were used.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution increases processing speed and density by enabling efficient data processing within memory, reducing the need for multiple SRAM bitcells and enhancing the semiconductor area necessary for implementing neurons, thereby overcoming the data-movement bottleneck in machine learning applications.
Implementation Method 1
a bias circuit including a charge pump capacitor
Implementation Method 2
a filter weight capacitor
Implementation Method 3
driving a current through a diode-connected transistor to charge a charge pump capacitor to a charge pump voltage
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.