Charge Pump Architecture Using NMOS Inter-Stage Connections
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Solution Overview
Problem
The Pelliconi charge pump architecture faces challenges due to parasitic resistance between boost capacitors and the inefficiency caused by the use of PMOS transistors, which have lower carrier mobility than NMOS transistors, leading to increased power consumption and reduced efficiency.
Innovation Solution
A new charge pump architecture that uses only NMOS transistors to connect boosting capacitors of adjacent stages and employs a delay in clock signals to reduce back charge conduction, replacing PMOS transistors with NMOS transistors to enhance performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If PMOS transistors are used to connect boost capacitors, then the charge pump can be constructed with standard transistor types, but the lower carrier mobility of PMOS transistors causes increased power consumption and reduced efficiency
Solution Approach 1:
The patent changes the key parameter of transistor type from PMOS to NMOS, exploiting the higher electron mobility of NMOS transistors to reduce power consumption and improve efficiency. This parameter change directly addresses the energy loss issue while maintaining manufacturability through standard CMOS processes.
Solution Approach 2:
Instead of using PMOS transistors as conventionally done in charge pumps, the patent inverts the approach by using NMOS transistors. This inversion leverages the superior electron mobility of NMOS devices to overcome the power consumption problem associated with PMOS transistors.
2Loss of energy
If standard charge pump architecture is used, then the circuit structure is simple and well-established, but parasitic resistance between boost capacitors reduces efficiency
Solution Approach 1:
The patent changes the transistor type parameter from PMOS to NMOS in the inter-stage connections, which reduces parasitic resistance and improves efficiency. This modification maintains the overall simple charge pump architecture while significantly impacting the resistive losses.
Solution Approach 2:
The patent applies local quality by specifically changing the transistor type only in the inter-stage connection regions where parasitic resistance is most problematic, while maintaining the standard architecture elsewhere. This targeted modification optimizes efficiency without requiring complete architectural redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively minimizes parasitic resistance and power consumption, improving the overall efficiency of the charge pump by utilizing NMOS transistors with higher carrier mobility and reducing back charge conduction effects.
Implementation Method 1
the inefficiency caused by the use of PMOS transistors, which have lower carrier mobility than NMOS transistors
Implementation Method 2
A charge pump circuit is a device using capacitors as energy-storage elements
Implementation Method 3
a clock signal CK and an inverted clock signal CKb, having inverted values with respect to the clock signal CK
Data Source
AI summary
Disclosed herein is a charge pump architecture in which boosting capacitors of adjacent stages are connected only by NMOS type transistors and comprising a first stage receiving a first voltage and outputting an internal voltage; a second stage receiving the internal voltage and outputting a second voltage at an output terminal, and an auxiliary stage connected to the output terminal, the first stage and second stage including a first type of MOS transistors transferring the voltage from input node internal boosting nodes and being cross-coupled; a second type of MOS transistors with their gate biased by a third type of MOS transistors and fourth type of MOS transistors; the third type of MOS transistors connecting the gate of the second type of MOS transistors; and the fourth type of MOS transistors connecting the gate of the second type of MOS transistors.