Low Voltage Charge Pump Stage With NMOS PMOS Segmentation
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Solution Overview
Problem
Conventional Dickson charge pump circuits face limitations in the number of cascaded stages due to voltage drop increases, requiring high-voltage transistors with thick oxide layers, making it difficult to design using thin oxide, low-voltage standard devices.
Innovation Solution
A charge pump stage design incorporating both NMOS and PMOS sections with transfer and coupling capacitors, stabilizing capacitors, and specific clock signal configurations to minimize voltage degradation across transistors, allowing the use of low-voltage devices and maintaining efficiency across multiple stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If multiple stages of Dickson charge pump are cascaded to increase output voltage, then the output voltage increases, but the voltage drop across each stage increases causing dramatic VT increase on last stages
Solution Approach 1:
The charge pump stage is segmented into separate NMOS and PMOS sections, each handling voltage pumping independently. This segmentation allows each transistor type to operate within its optimal voltage range, preventing cumulative voltage drops from affecting the entire stage uniformly.
Solution Approach 2:
The invention changes the operating parameters by using dual-polarity transistors (both NMOS and PMOS) with different threshold voltage characteristics. This allows the circuit to compensate for voltage drops by leveraging the complementary properties of the two transistor types, maintaining more stable operation across multiple cascaded stages.
2Reliability
If high voltage transistors with thick oxide layers are used to sustain large voltage drop, then reliability improves, but device complexity and difficulty of design using standard devices increases
Solution Approach 1:
The invention merges NMOS and PMOS transistors into a single integrated charge pump stage. This combination allows the circuit to achieve high voltage sustainability through the complementary action of two transistor types rather than relying on a single high-voltage transistor design, thereby maintaining compatibility with standard low-voltage fabrication processes.
Solution Approach 2:
The charge pump stage dynamically switches between NMOS and PMOS transistors using clock signals to control their operation. This dynamic switching allows each transistor type to operate in its optimal region, achieving reliable voltage pumping without requiring static high-voltage transistor structures with thick oxide layers.
3Ease of manufacture
If thin oxide low voltage standard devices are used, then device complexity decreases and ease of manufacture improves, but the maximum voltage drop is limited to VDD
Solution Approach 1:
The invention changes the voltage parameters by utilizing both NMOS and PMOS transistors in conjunction with coupling capacitors that store and transfer charge. This allows the circuit to achieve voltage drops greater than VDD by accumulating charge across multiple pumping cycles, while still using standard thin-oxide low-voltage transistors.
Solution Approach 2:
The charge pump maintains continuous useful action by using coupling capacitors to store energy during one phase and release it during another phase. This continuous charging and discharging process allows the circuit to build up voltage beyond the immediate VDD limit of individual transistors, enabling multiple stages to be cascaded effectively.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-stage charge pump achieves a high output voltage with minimal voltage loss, enabling efficient operation using low-voltage NMOS and PMOS devices without the need for high breakdown voltage devices, as demonstrated by achieving an output voltage of 10.83 volts with a power supply of 1 volt.
Implementation Method 1
A first transfer capacitor is coupled between the input node and a first clock input terminal and is configured to receive a first clock input signal
Implementation Method 2
A first coupling capacitor is coupled between the gate of the first NMOS transistor and a boost clock signal terminal that is configured to receive a boost clock signal
Implementation Method 3
A stabilizing capacitor is coupled between the intermediate is node and a ground voltage reference terminal
Data Source
AI summary
A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor.