Charge-Pump IC Pad Layout for Narrower Display Drivers
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Solution Overview
Problem
The challenge is to reduce the size of display drivers in integrated circuit devices while maintaining their functionality and mounting efficiency, as shrinking the devices using microfabrication technology leads to increased costs and difficulties in mounting due to narrower pitches and increased glass frame sizes, which complicates the layout and design of display panels in portable devices.
Innovation Solution
The solution involves an integrated circuit device design with first and second transistors connected by a charge-pump operation, an electrostatic discharge protection element, and a pad connected to a flying capacitor, where the pad overlaps part or all of the transistors and protection element, allowing for reduced wiring and increased efficiency, and the transistors can be disposed under the pad to minimize the device's width and enhance electrostatic discharge resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the integrated circuit device is shrunk by microfabrication technology, then the chip size is reduced, but it becomes difficult to mount the device and increases costs
Solution Approach 1:
The pad is positioned in an upper layer of the transistor structure, utilizing vertical stacking to reduce the horizontal footprint of the device. This dimensional reorganization allows compact integration while maintaining functional performance and mounting feasibility
2Area of moving object
If the chip size is reduced, then cost is reduced, but the glass frame size increases and creates unnecessary wiring regions
Solution Approach 1:
The pad structure is merged with the transistor active region, allowing the pad to overlap with the transistor in the vertical dimension. This integration eliminates separate wiring regions and reduces the overall chip area required for mounting pads
3Length of moving object
If the device width is reduced for compactness, then mounting is facilitated, but electrostatic discharge protection may be compromised
Solution Approach 1:
The electrostatic discharge protection element is nested within the vertical stack under the pad, utilizing the same footprint area. This nested configuration provides ESD protection functionality without increasing the horizontal device width
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in a narrower integrated circuit device that facilitates easier mounting and reduces costs by optimizing the layout and pitch, while maintaining the necessary width for circuit blocks and ensuring efficient signal transmission and electrostatic discharge protection.
Implementation Method 1
first and second transistors push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node by a charge-pump operation
Implementation Method 2
an electrostatic discharge protection element connected between the first power supply line and the connection node
Data Source
AI summary
An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.