Charge Pump Supply Clock Phase Interpolation Ripple Reduction
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Solution Overview
Problem
Existing charge pump designs in integrated circuits suffer from significant voltage ripple issues, which can lead to chip malfunction and reduced performance, particularly in high-performance applications, due to the fundamental frequency of voltage ripple being proportional to the load current and clock period, and current solutions like large decoupling capacitors or linear regulators are not always feasible.
Innovation Solution
The implementation of a voltage generator with multiple charge pumps and delay pipelines, where phase controllers induce timing offsets among the outputs of the delay stages, allowing multiple charge pumps to be triggered within the same unit delay but offset from each other, thereby reducing ripple effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock source drives multiple charge pump cells, then the circuit complexity is low, but the voltage ripple becomes significant
Solution Approach 1:
The single clock source is segmented into multiple clock phases using a delay line, where each phase drives a separate charge pump cell. This segmentation distributes the charge injection events across different time intervals, reducing the peak ripple current while maintaining the same overall charging function.
Solution Approach 2:
The charge pump cells operate in a periodic sequence with different phases, where each cell is activated at a different time within the clock period. This periodic staggering of operations smooths out the voltage ripple by spreading charge injection events across time, transforming the harmful concentrated ripple into a more uniform charging pattern.
2Object-generated harmful factors
If multiple delay pipelines with phase controllers are used to reduce ripple, then the voltage ripple is reduced, but the device complexity increases
Solution Approach 1:
The delay line structure serves multiple functions simultaneously: it generates phase-shifted clock signals, provides timing control for multiple charge pump cells, and inherently reduces voltage ripple through phase distribution. This multi-functionality reduces the need for separate ripple-reduction circuits, offsetting the added complexity with consolidated functionality.
Solution Approach 2:
The solution adds a time dimension to the charge pumping operation by introducing phase-shifted clock signals. Instead of all charge pumps operating simultaneously in the spatial domain, they are distributed across the time domain with controlled phase offsets, effectively using time as an additional dimension to reduce ripple without requiring parallel identical circuits.
3Object-generated harmful factors
If a large decoupling capacitor is added to reduce ripple, then the voltage ripple is reduced, but the chip area consumption increases
Solution Approach 1:
The mechanical approach of using large physical capacitors to filter ripple is replaced with an electrical timing approach using phase-shifted clock signals. Instead of passively filtering ripple with large decoupling capacitors, the invention actively prevents ripple generation by distributing charge injection events across multiple phases, substituting a compact timing control mechanism for bulky capacitive filtering.
Data Source
AI summary
A voltage generator may include a plurality of charge pumps, plural sets of delay pipelines and a phase controller. Given M delay pipelines having N stages each, there may be M*N charge pumps each having a triggering input coupled to a respective stage or a respective pipeline. The phase controller may include a plurality of phase control stages interconnecting among the delay pipelines to induce timing offsets among the outputs of the delay stage. In an alternate design, intermediate nodes among the pipeline's delay stages may be coupled to triggering inputs of a sub-set of the charge pumps. The phase controller may have a plurality of phase control stages coupled, respectively, between the intermediate nodes of the delay pipeline and intermediate nodes of the phase control stages may be coupled to triggering inputs of another sub-set of the charge pumps.