Charge Pump Voltage Control for Stable PLL Lock in FMCW Radar
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Solution Overview
Problem
In radar and wireless communication systems using Frequency Modulated Continuous Wave (FMCW), the signal quality is crucial for system performance, but existing Charge Pump-Phase Locked Loops (CP-PLL) face challenges in maintaining a locked state due to inconsistencies in the turned-on speeds of switch transistors, leading to net charges being non-zero when the PLL is locked.
Innovation Solution
The proposed solution involves a charge pump with a discharging circuit and a charging circuit, both connected to an output terminal, where the discharging circuit decreases the output terminal current under a first control signal, and the charging circuit increases it under a second control signal. A voltage control circuit adjusts the voltage of nodes in the discharging and charging circuits to maintain the locked state by ensuring the charging and discharging circuits are simultaneously turned on, thereby achieving a net charge of 0 or approximately 0 during the locked period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switch transistors are used in the charge pump to control charging and discharging, then the charge pump can regulate current flow, but the turned-on speeds of the switch transistors are inconsistent, leading to non-zero net charges when the PLL is locked
Solution Approach 1:
The patent introduces a feedback mechanism where the voltage control circuit continuously monitors the voltages at the first and second nodes and adjusts the gate voltages of the switch transistors accordingly. This feedback loop ensures that the charging and discharging currents are balanced, maintaining zero net charge during the locked state despite variations in transistor characteristics.
Solution Approach 2:
The patent dynamically adjusts the gate voltages of the switch transistors based on the detected voltage differences at the nodes. By changing the voltage parameters in real-time, the system compensates for the inconsistent turned-on speeds of the transistors, ensuring accurate charge balance and stable locked state operation.
2Manufacturing precision
If the charge pump operates with traditional switch transistor control, then the circuit structure remains simple, but the linearity of the charge pump deteriorates due to non-zero net charges
Solution Approach 1:
The patent introduces a voltage control circuit as an intermediary between the phase frequency detector and the switch transistors. This intermediary component processes the voltage information from the nodes and generates appropriate control signals, improving the linearity of the charge pump by ensuring precise control of the charging and discharging currents without significantly complicating the overall circuit structure.
3Reliability
If the charging and discharging circuits are not simultaneously turned on, then the charge pump can respond to phase errors, but the PLL may lose lock due to accumulated net charges
Solution Approach 1:
The patent implements periodic control of the charging and discharging operations through the voltage control circuit. By rhythmically adjusting the gate voltages based on the phase error signals and voltage feedback, the system ensures that charging and discharging occur in a coordinated periodic manner, preventing charge accumulation and maintaining stable locking over extended periods.
Data Source
AI summary
A charge pump, a phase-locked loop, a radar sensor, and an electronic device. The charge pump is applicable to the phase-locked loop. The charge pump comprises a discharging circuit and a charging circuit, both of which are connected to an output end of the charge pump. The discharging circuit reduces a current of the output terminal under control of a first control signal, the charging circuit increases it under control of a second control signal, the first control signal and the second control signal being corresponding to error signals between the two clock signals. The charge pump further comprises a voltage control circuit connected to a first node in the discharging circuit and/or a second node in the charging circuit to maintain the locked state of the phase-locked loop by controlling voltages of corresponding nodes, the first node and the second node being both connected to the output end.