Charge Pump Current Path Control for Low-Power PLL Lock
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Solution Overview
Problem
Modern phase-locked loops (PLLs) face challenges in reducing power consumption, particularly in charge pumps where constant current flow increases power consumption, necessitating a solution for low-power PLLs and related components.
Innovation Solution
A circuit and method that control current flow at an output node using multiple paths with switchable conductivity, managed by control signals generated from input signals, to reduce power consumption by varying the conductivity of conduction paths based on voltage thresholds and bias currents, thereby optimizing current flow timing and duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If constant current flows in the charge pump as the PLL approaches and achieves lock, then the PLL maintains stability and meets performance requirements, but power consumption significantly increases
Solution Approach 1:
The charge pump transitions from static constant current operation to dynamic variable current operation. The bias current supplied to the current source is dynamically adjusted based on the lock detection signal, allowing the charge pump to operate at full current during acquisition and reduce to minimal current during lock, thereby resolving the contradiction between maintaining stability and reducing power consumption
Solution Approach 2:
The patent changes the current parameter of the charge pump based on operational state. By modifying the bias current parameter in response to lock detection, the charge pump current is reduced when the PLL achieves lock, directly addressing the power consumption issue while maintaining operational reliability through parameter adaptation
2Use of energy by moving object
If the charge pump reduces current flow to lower power consumption, then energy efficiency improves, but response time may be compromised
Solution Approach 1:
The charge pump employs periodic full-current operation during phase acquisition followed by reduced current operation during lock. This periodic switching between high-performance mode and low-power mode ensures that fast response is available when needed while minimizing power consumption during steady-state operation
Solution Approach 2:
The lock detection mechanism performs preliminary assessment of PLL lock status to anticipate when current reduction is appropriate. By detecting lock conditions in advance, the system can proactively reduce current while maintaining response readiness, preventing response time degradation
Data Source
AI summary
A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a ground potential is varied. Optionally, the charge pump is disposed as part of a phase-locked loop (PLL), the input signals are produced by a phase/frequency detector, and current flow at the output node controls an oscillator element.