Charge Pump Circuit Segmentation for Power Efficiency
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Solution Overview
Problem
Charge pumps experience low power efficiency due to large current and parasitic capacitance at the output node, leading to high power consumption.
Innovation Solution
The charge pump design incorporates a circuit with NMOS and PMOS transistors in an inverter-like configuration, along with capacitors, to efficiently pump the input voltage to a higher output voltage, reducing energy wastage and increasing output current while minimizing current flow through parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a charge pump uses switching capacitors and a lower voltage at the input node to generate a higher voltage at the output node, then voltage transformation is achieved, but large current results in high power consumption
Solution Approach 1:
The charge pump is divided into multiple stages, with each stage containing series-parallel switched capacitor networks. This segmentation allows the pump to achieve voltage multiplication through incremental stages rather than a single large-current stage, reducing overall power consumption while maintaining output power.
Solution Approach 2:
The patent employs dynamic switching of capacitor configurations between series and parallel arrangements during different phases of operation. This dynamic reconfiguration optimizes current distribution across stages, enabling efficient voltage transformation while minimizing resistive losses and power consumption.
2Power
If the charge pump generates higher output voltage, then voltage pumping is achieved, but parasitic capacitance at the output node increases power consumption
Solution Approach 1:
The patent introduces intermediate nodes and distributed capacitor structures between the input and output. These intermediate elements act as mediators that distribute the voltage transformation across multiple smaller steps, reducing the current burden on any single node and minimizing the impact of parasitic capacitance at the output node.
Solution Approach 2:
The charge pump architecture extends the voltage transformation process into multiple temporal and spatial dimensions through phased switching operations. By distributing the voltage multiplication across different time phases and spatial locations (multiple stages), the patent reduces peak current demands and minimizes power loss due to parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves power efficiency by 35% to 50% and increases output current, achieving a voltage pump of 2 VDD to 3 VDD with reduced energy consumption and minimized current wastage.
Implementation Method 1
a first capacitive element coupled between the first node and the second node
Data Source
AI summary
In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of a first capacitive element. The second node is coupled with a first end of a second capacitive element. A first end of a first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive element and a first end of a second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element, and is configured to provide an output voltage.