Charge Pump Circuit Segmentation for Flash Memory Efficiency
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Solution Overview
Problem
Charge pump circuits in flash memory devices face challenges in increasing clock frequency due to complex clock control and suffer from decreased charge transfer efficiency due to high potential differences across transistors, which require high breakdown voltage and use diode-connected transistors that further reduce efficiency.
Innovation Solution
A charge pump circuit design that uses complementary clock signals to generate pumped voltage, with cascaded pump stages and anti-backflow circuits, where the potential differences across transistors are minimized, allowing for reduced breakdown voltage requirements and improved efficiency by using P-type and N-type transistors strategically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If four clock signals with different phases are used for charge pump operation, then pumped voltage can be generated, but clock control becomes complicated and clock frequency cannot be increased
Solution Approach 1:
The charge pump circuit is divided into multiple independent pump cells (first pump cell, second pump cell, third pump cell, fourth pump cell), each operating with a simple two-phase clock signal. This segmentation allows each cell to function independently with reduced clock control complexity while collectively achieving the pumped voltage generation function.
2Ease of manufacture
If diode-connected transistors are used for charge transfer, then device structure is simplified, but charge transfer efficiency decreases
Solution Approach 1:
The patent changes the operating parameters of the transistors by applying specific voltage potentials to their gates. The off-switch transistors have their gates connected to the output node, and the on-switch transistors have their gates connected to the input node, creating optimal voltage conditions that enhance charge transfer efficiency without requiring diode-connected configurations.
3Reliability
If high potential difference is applied across transistors to ensure proper switching, then switching reliability is improved, but breakdown voltage requirements increase
Solution Approach 1:
The patent employs equipotential connections where the gate of each off-switch transistor is connected to the output node (creating equipotential conditions during off-state), and the gate of each on-switch transistor is connected to the input node (creating equipotential conditions during on-state). This reduces potential differences across transistor terminals and lowers breakdown voltage requirements while maintaining switching reliability.
4Productivity
If clock frequency is increased to improve pumping speed, then productivity is improved, but clock margin becomes insufficient for proper switching
Solution Approach 1:
The patent uses periodic two-phase clock signals (CLK1 and CLK2) with complementary waveforms to drive the pump cells. This periodic action with clearly defined high and low phases provides sufficient clock margin for reliable transistor switching while maintaining high pumping speed. The anti-backflow circuits also operate periodically in sync with the clock phases.
Data Source
AI summary
Each of a plurality of pump stages has an input node and an output node and performs a charge pump operation in response to any one of the first and second clock signals. The plurality of pump stages include a first pump stage, in which a charge transfer transistor is connected between the input node and the output node. One end of a pump capacitor is connected to the output node, and the other end is supplied with one of the first and second clock signals corresponding to the first pump stage. A connection switcher connects to the gate of the charge transfer transistor any one of the output node of a pump stage which is supplied with one of the clock signals corresponding to the first pump stage and the input node of a pump stage which is supplied with the other clock signal not corresponding to the first pump stage and which is included in a pump stage row not including the first pump stage.