Low VIN Charge Pump Circuit With Segmented Paths
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Solution Overview
Problem
Conventional charge pump circuits are inefficient at low input voltages, which is a challenge for low power applications in integrated circuits, due to leakage and parasitic effects during operation.
Innovation Solution
The proposed charge pump circuit design includes two asynchronous charge transfer circuit paths with boost capacitors and charge switches, along with gate control circuits and clamping circuits, utilizing 4-phase clock signaling to minimize parasitic charge sharing and prevent reverse current, thereby enhancing efficiency and output voltage generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional charge pump circuits are used to boost supply voltage, then voltage boosting function is achieved, but circuit efficiency deteriorates due to leakage and parasitic effects at low input voltages
Solution Approach 1:
The charge pump circuit is divided into two independent charge transfer paths (first and second paths), each with its own boost capacitor, charge switch, and discharge switch. This segmentation allows independent optimization of each path to minimize parasitic effects and leakage, thereby improving overall circuit efficiency at low input voltages while maintaining the voltage boosting function.
2Use of energy by moving object
If charge pump circuit operates at low input voltage for low power applications, then power consumption is reduced, but circuit efficiency deteriorates due to increased parasitic effects
Solution Approach 1:
The circuit employs different switch types (NFETs and PFETs) in different locations within the charge transfer paths, with specific gate control arrangements optimized for low voltage operation. The gate control circuits provide localized voltage boosting to switch gates, ensuring low on-resistance and minimal parasitic effects at low input voltages, thereby maintaining high efficiency while enabling low power consumption operation.
3Power
If boost capacitors and charge switches are used to transfer charge, then output voltage is generated, but parasitic charge sharing occurs reducing efficiency
Solution Approach 1:
The gate control circuits are designed to pre-charge the gates of charge switches before the actual charge transfer operation begins. This preliminary action ensures that switches are fully enhanced and conduct with minimal on-resistance, preventing parasitic charge sharing between boost capacitors and ensuring efficient charge transfer to generate the desired output voltage.
4Power
If discharge switches are used to transfer charge to output, then voltage boosting is achieved, but reverse current flows reducing efficiency
Solution Approach 1:
The discharge switches are controlled with gate voltages that are preliminarily adjusted to maintain a forward bias condition throughout the charge transfer cycle. This preliminary anti-action prevents reverse current flow by ensuring the switches remain in a state that blocks reverse conduction, thereby maintaining high efficiency during voltage boosting operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a boosted output voltage approximately twice the input voltage with reduced parasitic effects and low ripple, making it suitable for low power applications by operating efficiently at low input voltages.
Implementation Method 1
a first boost capacitor coupled to a first clock input, a first charge switch coupled to a circuit input, and a first discharge switch coupled to a circuit output; a second charge transfer circuit path including a second boost capacitor
Data Source
AI summary
A charge pump circuit comprises a first charge transfer circuit path coupled including a first boost capacitor coupled to a first clock input, a first charge switch coupled to a circuit input, and a first discharge switch coupled to a circuit output; a second charge transfer circuit path including a second boost capacitor coupled to a second clock input, a second charge switch coupled to the circuit input, and a second discharge switch coupled to the circuit output; a first charge control circuit including a first gate switch coupled to a gate input of the first charge switch, and a first gate-drive capacitor coupled to the gate input of the second charge switch; and a second charge control circuit including a second gate switch coupled to a gate input of the second charge switch, and a second gate-drive capacitor coupled to the gate input of the first charge switch.


