Charge Pump Clock Control to Prevent Stop-State Through Current
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Solution Overview
Problem
Conventional voltage generation circuits in liquid crystal display devices experience a through current when the operation of a charge pump stops, due to the lack of a Hiz period during the switching of charge pumps.
Innovation Solution
A voltage generation circuit with a dual charge pump configuration, including a control circuit that synchronizes the enable signal with the clock signals to ensure that the charge pumps switch through a Hiz period even when stopping operation, thereby preventing through currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a dual charge pump circuit is used to generate power supply voltage, then voltage boosting capability is improved, but through current occurs when switching operation stops
Solution Approach 1:
The control circuit performs preliminary action by setting the enable signal to a low level before the clock signals transition, ensuring that the charge pump switches to charge state through the Hiz period in advance. This preliminary control prevents through current from occurring when the charge pump stops operating.
Solution Approach 2:
The control circuit uses feedback by monitoring the clock signal states and dynamically adjusting the enable signal timing. When detecting that the charge pump should stop operating, the control circuit responds by controlling the enable signal to ensure proper state transition, thereby preventing through current while maintaining voltage boosting capability.
2Loss of energy
If enable signal is supplied to stop charge pump operation, then power consumption is reduced, but through current occurs during state transition
Solution Approach 1:
The control circuit performs preliminary action by proactively controlling the enable signal to a low level before the charge pump completes its operation. This ensures that the transition to charge state occurs through the Hiz period, preventing through current while successfully stopping the charge pump to reduce power consumption.
Solution Approach 2:
The enable signal acts as an intermediary controlled by the control circuit to mediate the transition between operating and stopped states. By carefully timing the enable signal transition based on clock signal states, the control circuit ensures the charge pump passes through the Hiz period, preventing through current while achieving power savings.
3Object-generated harmful factors
If clock signals are delayed to create Hiz period, then through current is prevented during normal operation, but operation stopping becomes complex
Solution Approach 1:
The control circuit merges the Hiz period timing control with the enable signal control. Instead of separate delay circuits for Hiz period and enable control, the control circuit integrates both functions by coordinating the enable signal timing with the clock signal states, simplifying the overall control mechanism while preventing through current during both normal operation and stopping.
Solution Approach 2:
The control circuit uses feedback from the clock signal states to automatically adjust the enable signal timing. This feedback mechanism eliminates the need for complex external delay circuits, as the control circuit internally coordinates the Hiz period and operation stopping based on real-time clock signal monitoring, reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively prevents the generation of through currents when the charge pump operation stops, ensuring efficient and reliable voltage generation in liquid crystal display devices.
Implementation Method 1
a first capacitor and a second capacitor each having a predetermined capacitance
Data Source
AI summary
A charge pump circuit includes: first and second capacitors; a first switch element group turned on and off by a first clock signal and connecting a first voltage supply line and the first capacitor when turned on; a second switch element group turned on and off by the first clock signal and connecting a second voltage supply line and the second capacitor when turned on; and a third switch element group turned on and off by a second clock signal and connecting a voltage output line and the first and second capacitors when turned on. A control circuit controls a timing of a signal change of a first enable signal so that the signal levels of the first and second clock signals are fixed when the first and second switch element groups change from off to on, in response to stopping oscillating the first and second clock signals.