Charge Pump Verification Voltage Control for Memory Noise Reduction
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Solution Overview
Problem
In memory devices, the difference between specification and verification voltages can lead to unexpected peak currents, causing power and ground noise, which degrades the precision of erase and program operations.
Innovation Solution
A method and architecture for controlling the verification voltage in memory devices, where the charge pump circuit detects and pulls up the verification voltage only at the beginning of a verification cycle and stops when it reaches a predetermined level, allowing K data bits to be verified based on this voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the charge pump circuit continuously pulls up the verification voltage to ensure adequate voltage level for verification, then the verification operation can be performed, but unexpected peak currents are generated causing power noise and ground noise that degrades verification precision
Solution Approach 1:
The charge pump circuit operates periodically rather than continuously, activating only during specific time windows (e.g., during program/erase operations when verification voltage is needed) and remaining inactive during verification cycles. This periodic operation eliminates continuous peak currents while ensuring adequate voltage levels are maintained when required, thereby resolving the contradiction between reliable verification operation and precise measurement.
2Reliability
If the verification voltage is continuously controlled at the verification level to ensure adequate voltage for verification, then verification can be performed, but power noise and ground noise are generated making precision of verification degrade
Solution Approach 1:
The verification voltage is applied periodically rather than continuously - activated during program/erase operations and deactivated during verification cycles. This allows the verification operation to proceed with adequate voltage levels when needed, while eliminating the continuous noise generation that would otherwise degrade verification precision.
Solution Approach 2:
The charge pump circuit is activated in advance during program/erase operations to establish the verification voltage level before verification begins. This preliminary action ensures the voltage is ready and stable when verification starts, eliminating the need for continuous voltage control during verification that would generate noise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes power and ground noise by limiting the pumping operations, thereby improving the precision of memory verification without increasing additional costs.
Implementation Method 1
controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage
Data Source
AI summary
A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector.