Charge Pump Voltage Boosting in NAND Flash Memory
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Solution Overview
Problem
Conventional NAND flash memory devices require a large step-up factor in their boosting circuits to generate high voltages for data writing, erasure, and reading, leading to increased current consumption and longer operation times due to the need for a single power source, which results in inefficiencies and limitations in system design.
Innovation Solution
A nonvolatile semiconductor memory device and system that utilize a second power source higher than the standard power source to power a charge pump, allowing for a smaller number of boosting stages and enabling efficient voltage boosting, thereby reducing current consumption and operation time, while maintaining system design simplicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single power source is used for both logic circuit and charge pump, then system design is simplified, but the step-up factor of boosting circuit becomes large
Solution Approach 1:
The power source is divided into two separate inputs: a first power source for the logic circuit and a second power source for the charge pump. This segmentation allows each component to operate with its optimal voltage level, reducing the step-up factor required by the charge pump while maintaining simplified system design.
2Device complexity
If a single power source is used for both logic circuit and charge pump, then system design is simplified, but current consumption of boosting circuit increases
Solution Approach 1:
By separating the power source into two independent inputs, the charge pump can draw power directly from the second power source without requiring excessive current from a single unified source. This reduces the current consumption of the boosting circuit while maintaining design simplicity.
3Device complexity
If a single power source is used for both logic circuit and charge pump, then system design is simplified, but time required for data write, erase, and read increases
Solution Approach 1:
The dual power source configuration enables the charge pump to receive adequate power directly, reducing the time required for voltage boosting operations. This accelerates data write, erase, and read operations while keeping the system design simple through independent power inputs.
4Adaptability or versatility
If voltage is stepped down from 5V to 3.3V, then compatibility with 3.3V standard is achieved, but high voltage is still required for data write and erase
Solution Approach 1:
The system accepts two separate power inputs: a first power source at 3.3V for the logic circuit (maintaining compatibility) and a second power source at 5V for the charge pump (enabling high voltage generation). This segmentation allows the charge pump to generate the required 20V for data write and erase operations without compromising 3.3V standard compatibility.
5Power
If high voltage is boosted from regulated voltage, then data write and erase operations are enabled, but a large step-up factor is required
Solution Approach 1:
By providing a second power source at a higher voltage level (5V) specifically for the charge pump, the required step-up factor is reduced. This simplifies the boosting circuit design while still enabling the generation of high voltage (20V) necessary for data write and erase operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a second power source for the charge pump in NAND flash memory devices reduces the number of boosting stages, shortens data write and read times, and allows simultaneous initialization and boost operations, enhancing overall system efficiency and performance.
Implementation Method 1
a charge pump configured to supply power to the sense amplifiers, the column decoder, and the row decoder
Data Source
AI summary
A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.