Charge Pump Circuit for Flash Memory Voltage Generation
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Solution Overview
Problem
Flash memory devices require complex circuit constructions to generate positive and negative high voltages, which are necessary for programming and erasing operations, leading to increased complexity and inefficiency.
Innovation Solution
A charge pump and high voltage generator system that includes boost-up and boost-down pumps connected in series, utilizing pumping capacitors, gate pumping capacitors, charge transfer transistors, and gate control transistors to generate intermediate and final high voltages, simplifying the circuit structure and enabling precise voltage control during program and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate positive high voltage generator and negative high voltage generator are used, then both positive and negative high voltages can be generated, but the circuit construction becomes complicated
Solution Approach 1:
The charge pump circuit is designed to perform multiple functions: it can generate both positive high voltage (through boost-up pumps) and negative high voltage (through boost-down pumps) using a single integrated circuit structure. This multi-functional design eliminates the need for separate positive and negative high voltage generators, thereby simplifying the overall circuit construction while maintaining reliable voltage generation capability
Solution Approach 2:
The invention combines the previously separate positive high voltage generation circuit and negative high voltage generation circuit into a single unified charge pump circuit. By merging these functions into one circuit that can operate in both boost-up and boost-down modes, the patent reduces circuit complexity while achieving both voltage generation requirements
2Productivity
If multiple pumping operations are performed simultaneously, then both positive and negative high voltages can be generated efficiently, but voltage control precision decreases
Solution Approach 1:
The charge pump circuit employs dynamic control mechanisms where the pumping operations are adjusted based on real-time voltage feedback. The circuit can dynamically switch between boost-up and boost-down modes, and adjust pumping rates to maintain precise voltage control while achieving efficient voltage generation through coordinated pumping operations
Solution Approach 2:
The circuit incorporates feedback control mechanisms that monitor the generated voltages and adjust the pumping operations accordingly. This feedback system ensures that even when multiple pumping operations are performed simultaneously, the voltage control precision is maintained by making real-time adjustments to the pumping rates and timing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively generates the required high voltages, simplifying the circuit structure and ensuring precise voltage control for flash memory operations, thereby improving efficiency and reducing complexity.
Implementation Method 1
a first pumping capacitor configured to pump a first voltage of a first node, in response to a first clock signal
Implementation Method 2
a gate pumping capacitor configured to pump a second voltage of a second node, in response to a second clock signal
Implementation Method 3
a charge transfer transistor including a first source connected to a first one of a third node and the first node, a first gate connected to the second node, and a first drain connected to a remaining one of the first node and the third node
Implementation Method 4
a gate control transistor including a second source connected to the first one of the third node and the first node, a second gate connected to the remaining one of the first node and the third node, and a second drain connected to the second node
Data Source
AI summary
A charge pump includes a first pumping capacitor configured to pump a first voltage of a first node, in response to a first clock signal, a gate pumping capacitor configured to pump a second voltage of a second node, in response to a second clock signal, a charge transfer transistor including a first source connected to a first one of a third node and the first node, a first gate connected to the second node, and a first drain connected to a remaining one of the first node and the third node, a gate control transistor including a second source connected to the first one of the third node and the first node, a second gate connected to the remaining one of the first node and the third node, and a second drain connected to the second node, and a gate discharge or charge unit.