Charge Pump Circuit Wiring Resistance Optimization
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Solution Overview
Problem
In active matrix type liquid crystal display devices, unnecessary through currents flow due to increased rise and fall times of clocks in the power supply circuit, leading to reduced efficiency and increased power consumption.
Innovation Solution
The power supply circuit is designed with specific resistance ratios in its wiring to minimize transient through currents by using first and second charge transfer transistors connected in series, an output capacitor, and a flying capacitor, where the resistance of the wiring connecting the flying capacitor is larger than the other wirings, optimizing the clock inversion times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock inversion time is increased to allow complete charging/discharging of capacitors, then the charge transfer is more complete, but unnecessary through currents increase and power consumption increases
Solution Approach 1:
The patent changes the resistance parameter of the wiring connecting the flying capacitor to the charge transfer transistors. By optimizing this resistance value, the circuit achieves faster voltage transition during clock inversion, which suppresses through currents while ensuring complete charge transfer. This parameter optimization resolves the contradiction between power consumption and charge transfer completeness.
2Loss of energy
If the rise and fall times of clocks are reduced to suppress through currents, then power consumption decreases, but the charge transfer efficiency is reduced
Solution Approach 1:
The patent optimizes the resistance parameter of specific wirings in the charge pump circuit. By carefully selecting the resistance value of the wiring connecting the flying capacitor to the charge transfer transistors, the circuit achieves fast voltage transition that suppresses through currents while maintaining adequate charge transfer efficiency. This resolves the contradiction between energy loss and productivity.
3Loss of energy
If the resistance of the wiring connecting the flying capacitor is increased to optimize clock inversion, then through currents are suppressed, but the voltage drop increases
Solution Approach 1:
The patent optimizes the resistance parameter of the wiring connecting the flying capacitor to the charge transfer transistors. By selecting an optimal resistance value, the circuit achieves fast voltage transition that suppresses through currents while the output capacitor maintains the output electric potential. This parameter optimization resolves the contradiction between through current suppression and output power.
Solution Approach 2:
The patent introduces an output capacitor as an intermediary element that maintains the output electric potential despite voltage drops in the wiring. The output capacitor compensates for the voltage drop caused by the optimized resistance wiring, ensuring stable output power while maintaining the benefits of through current suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses unnecessary through currents, maintaining the output electric potential and reducing power consumption by ensuring quicker inversion of electric potentials during clock transitions.
Implementation Method 1
a flying capacitor having a first terminal connected with a connecting node between the first and second charge transfer transistors through a second wiring and a second terminal to which a clock is applied
Implementation Method 2
an output capacitor connected with a source of the second charge transfer transistor
Data Source
AI summary
An unnecessary through current is suppressed and insufficiency of an output electric potential and increase in power consumption are suppressed in a power supply circuit using a charge pump method. In order to suppress a reduction in an output electric potential VPP as well as suppressing transient through currents I1 and I2 when a clock DCCLK is inverted, resistances R1 of a wiring 11, R2 of a wiring 12 and R4 of a wiring 14 are set so as to satisfy relations R4>R1 and R4>R2. That is, the through currents I1 and I2 can be suppressed by reducing the resistances R1 and R2 so that electric potentials V1 and V2 are quickly inverted when the clock DCCLK is inverted. Also, the through current I1 can be suppressed to suppress the reduction in the positive output electric potential VPP by setting the resistance R4 to be larger than either of the resistances R1 and R2.