Charge-Pumped NMOS Transmission Gate for Low-Area Switching
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Solution Overview
Problem
Conventional power transmission gates require a larger footprint to achieve the same resistance as n-channel MOSFETs, leading to increased parasitic capacitance and size constraints in ICs, while also being inefficient in responding to rapid changes in input voltage.
Innovation Solution
A power transmission gate design incorporating a charge pump, an NMOS transistor, and a gate driver circuit that applies a drive voltage twice the input voltage, allowing for reduced size and lower parasitic capacitance while maintaining resistance and responsiveness to voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-channel MOSFET is used to achieve the same resistance as an n-channel MOSFET, then the resistance is matched, but the area must be approximately twice as large
Solution Approach 1:
The patent combines the p-channel MOSFET and n-channel MOSFET into a single integrated transmission gate structure where both transistors work together in parallel. This merging allows the p-channel device to be sized more efficiently (not twice as large) while still achieving the desired resistance characteristics through the combined conductive paths of both transistor types.
Solution Approach 2:
The patent changes the sizing parameters of the p-channel MOSFET relative to the n-channel MOSFET, using a width ratio (Wp/Wn) that is optimized for performance rather than the conventional 2:1 ratio. This parameter optimization allows the p-channel device to be smaller than twice the n-channel area while maintaining equivalent resistance, directly resolving the area contradiction.
2Area of moving object
If the transistor area is reduced to one NMOS size unit, then the footprint is minimized, but parasitic capacitance increases
Solution Approach 1:
The patent applies different design optimizations to different parts of the transmission gate. The p-channel MOSFET is specifically sized and configured with optimized dimensions (Wp and Lp) that balance the local electrical characteristics to minimize parasitic capacitance while maintaining low resistance. This localized optimization of transistor dimensions allows compact sizing without proportionally increasing parasitic effects.
Solution Approach 2:
The transmission gate uses dynamic control through complementary gate signals applied to the p-channel and n-channel MOSFETs. By dynamically switching the devices on and off together, the circuit achieves low effective resistance when conducting while minimizing the time that parasitic capacitances are charged, thereby reducing their harmful impact despite the compact size.
3Reliability
If conventional transmission gate design is used, then substrate diodes are reversely biased, but the response time to voltage changes is slow
Solution Approach 1:
The transmission gate structure is designed with pre-biased substrate connections and optimized transistor dimensions that prepare the devices for rapid switching. The p-channel and n-channel MOSFETs are configured with substrate terminals connected to appropriate supply potentials before switching occurs, ensuring that when voltage changes occur, the devices can respond immediately without delay from substrate diode effects or biasing transients.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables power transmission gates with a footprint of approximately one NMOS size unit to achieve the same resistance as conventional gates, with lower resistance per unit area and reduced parasitic capacitance, while responding quickly to input voltage changes.
Implementation Method 1
a charge pump coupled to the control terminal of the switch, wherein in response to the charge pump receiving an input voltage, the charge pump applies a drive voltage to the control terminal of the switch, wherein a voltage level of the drive voltage is larger than a voltage level of the input voltage
Data Source
AI summary
Described is a power transmission gate which includes a charge pump, an NMOS transistor, and a gate driver circuit configured to power (or bias or “drive”) a gate of the NMOS transistor. With this arrangement, a power transmission gate capable of achieving substantially the same resistance provided by prior art power transmission gates while having a footprint of just over one NMOS size unit is provided.