Charge-Recycling Clock Driver for Large Capacitive Loads
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Solution Overview
Problem
Conventional clock drivers for semiconductor memory devices face challenges in reducing power consumption and area occupation while maintaining high charge recycling efficiency and minimizing delay time, especially when driving large-capacity load capacitors.
Innovation Solution
A clock driver design incorporating a charge recycling switch and a switch controller with a configuration of NMOS or PMOS transistors and transmission gates, such as XOR or XNOR gates, to facilitate early charge recycling and reduce the number of logic gates, thereby enhancing power efficiency and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional inverter chains with increased W/L ratios are used to drive large-capacity load capacitors, then the driving capability is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements charge recycling by capturing charges discharged from the load capacitor through the NMOS transistor and transferring them to a charge storage capacitor. This recovers energy that would otherwise be wasted, directly reducing power consumption while maintaining the ability to drive large-capacity load capacitors
2Loss of energy
If charge recycling is implemented using complex structures or large areas, then charge recycling efficiency is improved, but device area and complexity increase
Solution Approach 1:
The patent extracts only the essential charge recycling function by using a simple NMOS transistor for charge capture and a dedicated charge storage capacitor, eliminating the need for complex logic gates and control circuits. This minimalistic approach achieves effective charge recycling with reduced device area and lower complexity
Solution Approach 2:
The NMOS transistor in the last stage serves multiple functions: it acts as the output driver for the inverter chain, the charge transfer switch for recycling, and the discharge path for the load capacitor. This multi-functionality eliminates the need for separate dedicated components, reducing overall circuit complexity
3Use of energy by moving object
If charge recycling is implemented using conventional methods with logic gates, then power efficiency is improved, but delay time increases
Solution Approach 1:
The charge storage capacitor is pre-charged to the appropriate voltage level before charge recycling is needed. When the NMOS transistor turns off, charges are immediately transferred to the pre-charged storage capacitor, enabling rapid charge recycling without waiting for charging operations, thus minimizing delay time
Data Source
AI summary
A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.