Charge-Redistribution Vector Matrix Multiplier for Low Power In-Memory Computing
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Solution Overview
Problem
Current matrix operation technologies, such as those using RRAM, face challenges with high power dissipation due to continuous current flow and limited resolution, requiring additional components like V-DACs and resulting in inefficient energy use and lower resolution capabilities.
Innovation Solution
A programmable in-memory computing device utilizing tuneable charge storage components and capacitors to perform vector-matrix multiplication, where each matrix memory component is connected in parallel and series to accumulate charge, reducing power dissipation and achieving higher resolution by leveraging capacitance-based charging instead of resistive elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RRAM devices are used for matrix operations with continuous current flow, then matrix multiplication can be performed, but power dissipation increases significantly
Solution Approach 1:
The patent applies periodic action by using time-multiplexed charging phases. The charge storage component is charged during a specific time window when the vector signal is applied, and remains charged during subsequent phases. This eliminates the need for continuous current flow, reducing power dissipation while maintaining computational capability through periodic charge redistribution.
Solution Approach 2:
The patent substitutes the resistive current-based mechanism (RRAM) with a capacitive charge-based mechanism. Instead of using continuous current flow through resistive elements, the system uses charge accumulation in capacitors during discrete time phases, replacing the mechanical/electrical current flow with electrical charge storage and redistribution.
2Productivity
If RRAM devices are used for matrix operations, then computation can be performed, but resolution is limited to maximum 3-4 bits
Solution Approach 1:
The patent applies parameter changes by using the capacitance value as a tunable parameter that can be precisely controlled. The charge storage component's capacitance can be adjusted to represent different weight values with high precision, enabling resolution beyond the 3-4 bit limitation of RRAM devices. This allows for more precise representation of matrix weights.
3Measurement precision
If separate V-DAC is required for each vector element with continuous current flow, then accurate vector input is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent applies universality by using a single shared charge storage component that can be charged by different vector signals in different time phases. Instead of requiring separate V-DACs for each vector element, the system uses one charge storage component that serves multiple functions through time-multiplexed charging, reducing device complexity while maintaining input accuracy.
Solution Approach 2:
The patent uses periodic action with time-multiplexed charging phases to replace multiple simultaneous V-DACs. The charge storage component is charged sequentially in different time windows corresponding to different vector elements, eliminating the need for parallel V-DACs and reducing overall device complexity.
4Productivity
If RRAM devices are used for matrix operations, then computation can be performed, but chip area increases due to required components
Solution Approach 1:
The patent extracts and eliminates unnecessary components from the RRAM-based architecture. By removing the need for continuous current flow, separate V-DACs for each element, and complex switching networks, the system achieves matrix operations with significantly reduced chip area while maintaining computational functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes power consumption and enhances resolution by using small capacitors, reducing chip area requirements and achieving higher precision in matrix product calculations compared to RRAM-based solutions.
Implementation Method 1
Each matrix memory component of the storage component matrix comprises a tuneable charge storage component that is connected between the vector input device and a reference potential and that is tuneable by the respective matrix input signal to assume a capacitance value uniquely corresponding to the respective input matrix value
Implementation Method 2
a vector input switch for controlling provision of the respective analog input vector signal for charging the charge storage component of the matrix component to a charge amount representing a mathematical product of the respective input vector value and the respective input matrix value
Implementation Method 3
The matrix memory components of a given matrix component column are each followed by a component product accumulation switch for controlling an output of the charge amount from the respective matrix memory component, and are arranged in a parallel connection with each other and commonly connected in a series connection with a respective column summation charge storage component that is configured to accumulate the respective charge amounts output from the charge storage components so as to generate a column summation output voltage
Data Source
Figure 1a~2b
Figure 3a~3b
Figure 4a~4b
AI summary
For performing in-memory multiplication of an input vector with an input matrix a storage component matrix comprises matrix memory components with a charge storage component that is tuneable by a respective matrix input signal to assume a capacitance value uniquely corresponding to an input matrix value. A vector input switch controls provision of the analog input vector signal for charging the charge storage component of the matrix memory component to a charge amount representing a mathematical product of the respective input vector value and the respective input matrix value. The matrix memory components of a column are arranged in parallel connection with each other and commonly connected in series connection with a column summation charge storage component which accumulates the charge amounts output from the charge storage components to generate a column summation output voltage indicative of a sum of the component products.