Charge-Reservoir Logic Gate for Low-Power Single-Device Switching
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Solution Overview
Problem
Conventional CMOS logic gates require pairs of n-type and p-type semiconductor devices, leading to inefficiencies in power dissipation and device count, with nMOS performance often being superior to pMOS due to electron mobility differences.
Innovation Solution
A logic gate design utilizing a charge reservoir layer between two charge accepting layers, where mobile charge carriers are transferred based on input voltage, reducing the need for two types of devices and minimizing simultaneous conductivity states, thus reducing power dissipation and device count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CMOS logic gates use pairs of nMOS and pMOS devices, then logical functions can be implemented, but device count increases and power dissipation worsens
Solution Approach 1:
The patent combines the functions of pMOS and nMOS devices into a single semiconductor device with dual charge accepting layers. The first charge accepting layer handles one type of charge carrier while the second layer handles the opposite type, merging what were previously two separate devices into one integrated structure. This reduces device count while maintaining the ability to implement logical functions.
Solution Approach 2:
The single semiconductor device performs multiple functions that previously required two separate devices. By incorporating both charge accepting layers within one device structure with shared source and drain regions, the device can operate in different modes (first mode with first charge carriers, second mode with second charge carriers) to implement various logical functions, achieving multi-functionality with reduced device count.
2Productivity
If conventional CMOS logic gates use pairs of nMOS and pMOS devices, then logical functions can be implemented, but power dissipation increases due to simultaneous conductivity
Solution Approach 1:
The device dynamically switches between different operational modes by controlling which charge accepting layer receives charge carriers. In the first operational mode, the first charge accepting layer is active while the second is inactive. In the second operational mode, the roles reverse. This dynamic switching ensures that only one charge accepting layer conducts at a time, preventing simultaneous conductivity and reducing power dissipation while maintaining logical function implementation.
3Productivity
If pMOS devices are used in CMOS gates, then logical functions can be implemented, but performance is limited by lower electron mobility compared to nMOS
Solution Approach 1:
The device dynamically switches between two operational modes, allowing it to utilize the higher mobility charge carriers in either the first or second charge accepting layer depending on the required logical function. This dynamic capability enables the device to achieve performance levels comparable to or exceeding traditional nMOS-based circuits, while maintaining the ability to implement all necessary logical functions that would otherwise require pMOS devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed logic gate operates symmetrically with reduced power dissipation and device count, enhancing compactness and scalability, while maintaining efficient logical operations.
Implementation Method 1
the charge reservoir layer comprising a potential well having a lowest energy state for mobile charge carriers that is at a lower energy than the lowest energy state for mobile charge carriers of both the first and second charge accepting layers
Data Source
AI summary
There is provided a logic gate comprising a semiconductor device. The semiconductor device includes a charge reservoir layer disposed between a first charge accepting layer and a second charge accepting layer. The first charge accepting layer defines a first current flow path that is connected to a common output contact at one end and a drive contact at the other end. The second charge accepting layer defines a current flow path that is connected to the common output contact at one end and a ground contact at the other end. The charge reservoir layer comprises a potential well having a lowest energy state for mobile charge carriers that is at a lower energy than the lowest energy state for mobile charge carriers of both the first and second charge accepting layers. The logic gate further comprises a control gate and a ground electrode that are separated from the charge accepting layers by non-conducting layers. The control gate and the ground electrode are configured to apply an input voltage across the semiconductor device, such that mobile charge carriers confined within the charge reservoir layer are transferred to the first charge accepting layer at a first applied input voltage and transferred to the second charge accepting layer at a second applied input voltage.