Charge-Retaining Transistor With Selective Charge-Trapping Islands
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Solution Overview
Problem
The challenge in flash memory fabrication is to reduce the horizontal area occupied by memory cells while maintaining or reducing the vertical thickness, which is typically achieved by transitioning from horizontally extending to vertically extending memory cell strings, but this often results in increased vertical thickness and complexity in substrate usage.
Innovation Solution
The development of a charge-retaining transistor with a control gate, inter-gate dielectric, charge-storage node, tunnel dielectric, and charge-trapping islands, along with an oxidation-protective material, which are strategically positioned and fabricated using techniques like atomic layer deposition and chemical vapor deposition to optimize the substrate usage and reduce horizontal area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertically extending memory cell strings are used, then horizontal area occupation is reduced, but vertical thickness increases
Solution Approach 1:
The patent transitions from horizontally extending memory cell strings to vertically extending memory cell strings, changing the primary dimension of memory array expansion from horizontal plane to vertical direction. This dimensional change allows dense packing of memory cells in the vertical direction while minimizing horizontal footprint, directly resolving the contradiction between reducing horizontal area and managing vertical thickness.
2Area of stationary object
If vertically extending memory cell strings are used, then horizontal area occupation is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory array into multiple horizontal layers stacked vertically, with each layer containing memory cells that extend in the horizontal direction. This segmentation approach allows the complex three-dimensional structure to be managed as a series of simpler two-dimensional layers, reducing substrate usage complexity while maintaining vertical extension for horizontal area reduction.
Solution Approach 2:
The patent implements nested structures where tunnel dielectric and charge-trapping layers are positioned within and around the memory cell string structure. The oxidation-protective material further nests within this configuration, creating a compact multi-layered arrangement that reduces horizontal area occupation while organizing the complex substrate usage in a systematic nested pattern.
3Ease of manufacture
If conventional horizontal memory cell strings are used, then fabrication is simpler, but horizontal area occupation increases
Solution Approach 1:
The patent extends memory cell strings in the horizontal direction within each layer, utilizing the horizontal dimension for memory cell arrangement rather than vertical stacking. This approach maintains fabrication simplicity by working with planar structures while reducing horizontal area occupation through multi-layer vertical stacking, effectively trading vertical space for horizontal area reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a more efficient use of substrate space, enabling the formation of vertically extending memory cell strings that reduce horizontal area occupation while maintaining or improving vertical thickness, thus enhancing the density and performance of flash memory arrays.
Implementation Method 1
an oxidation-protective material alongside those islands
Implementation Method 2
tunnel dielectric alongside the charge-storage node
Data Source
AI summary
A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed.