Charge Retention Circuit Counter for Electronic Disturbance Protection
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Solution Overview
Problem
Conventional protection mechanisms for electronic circuits fail to distinguish between incidental malfunctions and fraudulent attacks, leading to difficulties in determining the appropriate response, as they often require different actions for each scenario.
Innovation Solution
A method using a charge retention circuit with capacitive elements and transistors to detect disturbances by incrementing or decrementing a counter, which automatically resets over time, allowing for differentiation between incidental and fraudulent malfunctions by blocking access to critical processes when a threshold is exceeded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional protection mechanisms are used to detect disturbances in electronic circuits, then security protection is provided, but the ability to distinguish between incidental malfunctions and fraudulent attacks is lost
Solution Approach 1:
The patent applies the dynamics principle by making the counter automatically reset after a predetermined time period, transforming the static counter into a dynamic element that adapts its state over time. This temporal dimension allows the system to differentiate between single incidents and repeated attacks, resolving the contradiction between providing security protection and accurately measuring disturbance types.
Solution Approach 2:
The patent introduces a counter as an intermediary element between the disturbance detection mechanism and the response action. This counter mediates by accumulating disturbance events and comparing against a threshold, enabling the system to distinguish between incidental malfunctions and fraudulent attacks, thus improving measurement precision while maintaining security protection.
2Ease of operation
If the counter is manually reset, then the system can continue operation after malfunctions, but the automatic reset capability is lost
Solution Approach 1:
The patent applies the self-service principle by enabling the counter to automatically reset itself after a predetermined time period without external intervention. This automation eliminates the need for manual reset operations while maintaining the system's ability to continue operation after malfunctions, thus improving automation extent while preserving ease of operation through the automatic time-based reset mechanism.
3Reliability
If the counter threshold is set low for high security, then fraudulent attacks are blocked more effectively, but incidental malfunctions may cause unnecessary blocking
Solution Approach 1:
The patent applies dynamics by implementing a time-based automatic reset mechanism that allows the system to adapt its response based on the temporal pattern of disturbances. This enables the system to maintain high security thresholds while automatically recovering from incidental malfunctions, thus preserving both fraud prevention effectiveness and response appropriateness.
Solution Approach 2:
The patent changes the parameter of counter reset behavior from static (manual reset only) to dynamic (automatic time-based reset). This parameter change allows the system to maintain strict threshold settings for security while automatically adapting to incidental malfunctions through time-based reset, resolving the contradiction between security effectiveness and response versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively differentiates between incidental and fraudulent malfunctions, enabling appropriate countermeasures such as blocking access to sensitive data to prevent fraud, while allowing the circuit to restart after incidental malfunctions.
Implementation Method 1
a charge retention circuit comprising at least one capacitive element
Implementation Method 2
at least one first capacitive element exhibiting a leakage through its dielectric space
Data Source
AI summary
A method and a circuit for protecting data contained in an electronic circuit against a disturbance of its operation, in which a detection of a disturbance conditions the incrementing or the decrementing of a counter over at least one bit, the counter being automatically reset at the end of a time period independent from the fact that the circuit is or not powered.


