Time-Interleaved Charge Sampler for Low-Power 5G RF Filtering
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Solution Overview
Problem
Current RF receiver designs for 5G communication systems face challenges in power consumption and area usage due to the need for high-order filters and buffers for anti-aliasing and baseband filtering, particularly with millimeter wave signals, which incur significant power and noise penalties.
Innovation Solution
A time-interleaved current-mode charge sampler is introduced, which eliminates power-hungry voltage-mode buffers and filters by providing inherent anti-alias filtering, reducing power consumption and area usage while scaling with sample rate, and relaxing baseband filter constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-order filters and buffers are used for anti-aliasing and baseband filtering in 5G receivers, then filtering performance is improved, but power consumption and area usage increase significantly
Solution Approach 1:
The patent changes the operating parameters by using time-interleaved sampling with multiple sub-ADCs operating at lower individual rates to achieve the equivalent of a high-rate single ADC. This parameter change allows filtering to be performed in the digital domain with relaxed requirements, reducing the need for high-order analog filters and power-hungry buffers while maintaining the same filtering performance.
Solution Approach 2:
The patent segments the single high-rate ADC function into multiple lower-rate sub-ADCs operating in parallel with time-interleaved sampling. This segmentation distributes the filtering and processing load across multiple channels, allowing each channel to use simpler, lower-power filters while achieving the same overall filtering performance through digital signal processing.
2Reliability
If high-order filters and buffers are used for anti-aliasing and baseband filtering in 5G receivers, then filtering performance is improved, but area usage increases significantly
Solution Approach 1:
The patent changes the sampling rate parameter for each sub-ADC, allowing them to operate at lower individual rates. This parameter change reduces the order of filters needed in each channel and eliminates the need for large buffers, significantly reducing the area required while maintaining filtering performance through time-interleaved processing.
Solution Approach 2:
The patent segments the filtering function across multiple time-interleaved channels, where each channel performs filtering at a lower rate. This segmentation reduces the area required for filters and buffers in each individual channel, and the overall filtering performance is achieved through digital processing of the combined time-interleaved output.
3Power
If voltage-mode buffers are used in conventional ADC architectures, then signal driving capability is maintained, but power consumption increases
Solution Approach 1:
The patent substitutes voltage-mode buffering with current-mode signal processing throughout the time-interleaved ADC architecture. Current-mode operation provides inherent signal driving capability without requiring power-hungry voltage-mode buffers, as current signals can be directly summed and processed in the digital domain after conversion, eliminating the need for intermediate voltage buffering stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers power and area consumption while maintaining filtering performance, enhancing the scalability and efficiency of RF receivers for 5G systems by using current-mode filters and inherent anti-aliasing in the time-interleaved charge sampler.
Implementation Method 1
sampling a current-mode input signal at a charge sampler switch to integrate an analog value of the current-mode input signal in a charge sampler capacitor
Data Source
AI summary
A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.