Charge-Scaling Capacitor DAC for Process-Variation Linearity
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Solution Overview
Problem
Modern digital-to-analog converters (DACs) are sensitive to semiconductor manufacturing process errors, leading to performance variability and non-linearities in signal conversion.
Innovation Solution
A two-stage charge-scaling DAC design utilizing unit-cell capacitors with relative capacitance values, where capacitors are coupled to either ground or a reference voltage based on digital signal bits, reducing the impact of manufacturing errors and minimizing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DAC designs are used, then manufacturing simplicity is maintained, but performance is sensitive to fabrication errors
Solution Approach 1:
The patent changes the critical parameter from absolute capacitance values to relative capacitance ratios. By designing the DAC to depend on the ratio between capacitors in the same array rather than absolute values, fabrication errors affect all capacitors uniformly and cancel out in the ratio calculation, thereby improving performance stability without requiring higher manufacturing precision
Solution Approach 2:
The patent uses capacitors with identical geometric structures and material compositions within each array, ensuring they experience the same fabrication conditions. This homogeneity causes systematic errors to affect all capacitors equally, making the relative ratios immune to process variations and improving reliability
2Measurement precision
If high-resolution DAC designs are implemented, then conversion precision is improved, but layout area increases
Solution Approach 1:
The patent segments the capacitor arrays into multiple groups with different capacitance values (e.g., C, 2C, 4C, 8C) corresponding to different bit weights. This segmentation allows high-resolution conversion to be achieved through combinatorial switching of segmented capacitor groups rather than using a single large capacitor array, thereby reducing the total layout area while maintaining conversion precision
Solution Approach 2:
The patent introduces a temporal dimension by using switching arrays to dynamically connect different capacitor groups to the output at different times based on the digital input bits. This dimensional approach allows high-resolution conversion to be achieved sequentially rather than requiring all capacitors to be simultaneously connected, reducing the required layout area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves reduced non-linearities and improved performance by using capacitors with accurate relative capacitance values, enhancing the conversion of digital signals to analog signals with increased resolution and reduced sensitivity to manufacturing errors.
Implementation Method 1
a scaling capacitor coupled between the first and the second circuit node... the scaling capacitor has a capacitance value that equals a unit capacitance value
Implementation Method 2
a first array of capacitors coupled to the first circuit node... selectively couple the first array of capacitors to either ground or a reference voltage
Data Source
AI summary
A digital-to-analog converter is disclosed for converting a digital signal into its analog equivalent. The digital-to-analog converter includes a two switches capable of coupling circuit nodes to ground, a scaling capacitor having a capacitance value that equals a unit capacitance value, a first array of capacitors coupled to the first circuit node and a first switching array which couples the first array of capacitors to either ground or a reference voltage depending on the digital values of the least significant bits of the digital word being converted, a second array of capacitors coupled to the second circuit node and a second switching array which couples the second array of capacitors to either ground or the reference voltage depending on the digital values of the most significant bits of the digital word being converted.