Charge-Sharing ADC Circuit for Alias Rejection Without Higher Sampling
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Solution Overview
Problem
Existing electronic devices face challenges in designing analog-to-digital converters that effectively reject high-frequency jammers without increasing power consumption or design complexity, as current solutions either require large filter circuitry, substantial power, or high sampling rates.
Innovation Solution
The implementation of charge sharing techniques within analog-to-digital converters using multiple capacitors and switches to filter and decimate analog signals, allowing for alias rejection by averaging samples and adjusting capacitance to attenuate various frequencies without changing the sampling rate, thereby conserving power and space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If rejection or filter circuitry is used to attenuate jammers, then alias rejection is improved, but device size and power consumption increase
Solution Approach 1:
The patent combines the anti-aliasing filter and sample-and-hold circuit into a single integrated structure where capacitors serve dual purposes: filtering high-frequency jammers and holding sampled voltage values. This merging eliminates the need for separate rejection circuitry, reducing power consumption and device size while maintaining alias rejection capability.
Solution Approach 2:
The capacitors in the patent perform multiple functions simultaneously: they act as anti-aliasing filters to attenuate high-frequency jammers, serve as sample-and-hold capacitors to store voltage values, and participate in charge-sharing to generate averaged output. This multi-functionality removes the need for dedicated rejection circuitry, thereby reducing power consumption and device complexity.
2Reliability
If rejection or filter circuitry is used to attenuate jammers, then alias rejection is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the anti-aliasing filter and sample-and-hold circuit into one integrated structure using shared capacitors and switches. This consolidation reduces the number of discrete components and simplifies the overall circuit architecture, lowering device complexity and manufacturing cost while maintaining effective alias rejection.
Solution Approach 2:
By designing capacitors and switches to serve multiple functions (filtering, sampling, holding, and charge-sharing), the patent eliminates the need for separate rejection circuitry. This multi-functionality approach reduces component count and circuit complexity, making the device easier to manufacture and more cost-effective.
3Reliability
If sampling rate is increased to prevent aliasing, then alias rejection is improved, but power consumption and design complexity increase
Solution Approach 1:
The patent changes the approach from increasing the sampling rate to modifying the filter characteristics. By adjusting the RC time constant (through capacitor selection or switching different capacitor values), the anti-aliasing filter effectively attenuates high-frequency jammers at the existing sampling rate, avoiding the power consumption and complexity associated with higher sampling rates.
4Reliability
If sampling rate is increased to prevent aliasing, then alias rejection is improved, but design complexity increases
Solution Approach 1:
Instead of increasing the sampling rate, the patent changes the filter parameters (RC time constant) to achieve effective alias rejection at the existing sampling rate. This approach avoids the increased design complexity associated with high-speed sampling circuits while maintaining reliable alias rejection through optimized filter characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides effective alias rejection by attenuating high-frequency jammers while maintaining a stable sampling rate, reducing power consumption, and utilizing existing components, thus enhancing the efficiency and cost-effectiveness of electronic device design.
Implementation Method 1
By sharing charge across two or more capacitors, multiple samples of the analog signal are averaged
Data Source
AI summary
An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.