Charge Sharing Circuit Reducing Level Translation Chip Area
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Solution Overview
Problem
The existing charge sharing circuits in display devices require a large number of level translation circuits, occupying a significant chip area, which is inefficient.
Innovation Solution
A charge sharing circuit that includes a control unit and a switch unit, where the control unit is connected to the output control ends of two clock signal generation units, and the switch unit connects the clock signal output ends of these units under an on control signal, reducing the need for level translation circuits and saving chip space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If level translation circuits are used to control sharing switch on and off states, then the charge sharing circuit can function properly, but a large quantity of level translation circuits are adopted and a large area of chip is occupied
Solution Approach 1:
The patent extracts and removes the level translation circuits from the charge sharing circuit. Instead of using traditional level translation circuits to control the sharing switch, the invention directly uses the output control signal from the clock signal generation unit to control the sharing switch, eliminating the need for separate level translation circuits and significantly reducing chip area occupation.
Solution Approach 2:
The output control signal from the clock signal generation unit serves multiple functions: it controls the output of the first voltage signal and simultaneously controls the on and off states of the sharing switch. This multi-functionality eliminates the need for dedicated level translation circuits, reducing both component quantity and chip area while maintaining proper circuit functionality.
Data Source
AI summary
A charge sharing circuit, a charge sharing method, a display driving module and a display device are provided. The charge sharing circuit includes a control unit and a switch unit. The control unit is electrically connected to first output control ends of two clock signal generation units, and configured to provide, when a first output module controls to not output a first voltage signal under the control of a first output control signal, an on control signal to the switch unit through a control signal output end. The switch unit is configured to control clock signal output ends of the two clock signal generation units to be electrically connected to each other under the control of the on control signal.