Charge Sharing Memory Unit for Multi-Bit CNN Computing
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Solution Overview
Problem
Conventional computing-in-memory (CIM) systems for multi-bit convolutional neural networks face challenges with high power consumption, timing variations, sensing errors, area overhead, and increased latency due to high bit precision requirements, especially in static random access memory (SRAM) structures.
Innovation Solution
A memory unit and array structure for multi-bit CNN based CIM applications utilizing charge sharing, controlled by word lines, enable signals, and switching signals, which includes memory cells and computational cells that perform multiply-and-accumulate operations without additional capacitance or transistors, allowing for parallel processing and efficient energy use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high bit precision is used to achieve higher accuracy in CNN applications, then inference accuracy is improved, but operation speed decreases and energy efficiency deteriorates
Solution Approach 1:
The patent merges memory and computing functions into a single integrated structure where memory cells perform both storage and MAC operations. This integration eliminates the need for separate high-precision computing units, enabling multi-bit operations to be performed efficiently within the memory array itself, thus maintaining accuracy while improving speed and energy efficiency
Solution Approach 2:
The patent changes the operational parameters of the memory cell by utilizing charge sharing mechanisms and controlled discharge patterns. By adjusting the number of discharged memory cells and controlling the duration of discharge, the system can perform multi-bit operations with effective bit precision matching the input bit width, achieving high accuracy without the overhead of traditional high-precision arithmetic units
2Productivity
If the number of operations is increased in one cycle to decrease latency, then productivity is improved, but device complexity increases
Solution Approach 1:
The memory cell is designed to perform multiple functions: storing weights, performing MAC operations, and supporting multi-bit input processing. By making the memory cell universal, the system can increase the number of operations per cycle without adding separate functional units, thus improving productivity while maintaining relatively simple device structure
Solution Approach 2:
The patent introduces dynamic control mechanisms including adjustable discharge durations, configurable numbers of discharged memory cells, and controllable charge sharing ratios. These dynamic parameters allow the system to adapt the number of operations per cycle based on computational needs, achieving high productivity without requiring a statically complex circuit design
3Extent of automation
If conventional CIM SRAM structure discharges bit lines to perform MAC operation, then computing function is achieved, but power consumption increases and timing variation vulnerability increases
Solution Approach 1:
The patent employs periodic discharge patterns where memory cells are discharged in controlled time intervals rather than continuously. By regulating the discharge duration and timing, the system performs MAC operations with reduced power consumption and improved timing stability, as the periodic action allows for controlled charge sharing and accumulation without sustained high current draw
4Productivity
If charge sharing is performed to increase operations, then productivity is improved, but global capacitance decreases sensing margin and causes sensing errors
Solution Approach 1:
The patent applies local quality by performing charge sharing within localized groups of memory cells rather than globally across the entire array. By confining charge sharing to local regions and using local bit lines for sensing, the system maintains adequate sensing margins while still achieving improved productivity through parallel multi-bit operations
5Measurement precision
If conventional CIM SRAM structure uses extra 4× and 1× capacitance or transistors for weight combination, then weight precision is improved, but area overhead increases
Solution Approach 1:
The memory cell structure is designed to perform weight combination operations using its own intrinsic capacitance and charge storage capabilities, without requiring external or additional capacitance elements. The weight combination is achieved through controlled charge sharing among the memory cells themselves, eliminating the need for extra area-consuming capacitance or transistor structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances operation speed, reduces area and energy consumption, and prevents write disturb issues, enabling efficient multi-bit operations without extra capacitance or transistors, thereby improving energy efficiency and reducing latency.
Implementation Method 1
a charge sharing is performed, a global capacitance may decrease the influence of a local capacitance so as to lower the sensing margin and cause sensing error
Data Source
AI summary
A memory unit includes at least one memory cell and a computational cell. The at least one memory cell stores a weight. The at least one memory cell is controlled by a first word line and includes a local bit line transmitting the weight. The computational cell is connected to the at least one memory cell and receiving the weight via the local bit line. Each of an input bit line and an input bit line bar transmits a multi-bit input value. The computational cell is controlled by a second word line and an enable signal to generate a multi-bit output value on each of an output bit line and an output bit line bar according to the multi-bit input value multiplied by the weight. The computational cell is controlled by a first switching signal and a second switching signal for charge sharing.