Charge-Sharing PLL Locking for Low-Jitter Fractional-N Synthesis
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Solution Overview
Problem
Current phase-locked loop (PLL) technologies, particularly in 5G millimeter-wave frequency generation, face challenges with high in-band phase noise, jitter, and power consumption, limiting their effectiveness and robustness over process, voltage, and temperature variations, and are restricted to integer-N operation.
Innovation Solution
A phase-locked loop (PLL) with a charge-sharing locking mechanism, incorporating a voltage pre-setting stage, a shared capacitive load, and a switching network that selectively connects the voltage pre-setting stage and the oscillator to correct phase errors, enabling fractional-N operation and reducing power consumption while maintaining robustness against PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sub-sampling PLL is used to achieve ultra-low jitter, then jitter performance is improved, but power consumption increases significantly
Solution Approach 1:
The locking mechanism is segmented into two distinct phases: voltage pre-setting phase and charge-sharing locking phase. This segmentation allows the system to achieve ultra-low jitter through precise voltage control while minimizing power consumption by activating components only when necessary rather than continuously
Solution Approach 2:
The switching network operates periodically, connecting the voltage pre-setting stage to the capacitive load during voltage pre-setting phase and connecting the capacitive load to the oscillator during charge-sharing locking phase. This periodic action reduces average power consumption while maintaining ultra-low jitter performance
2Measurement precision
If injection locking is used for frequency generation, then frequency accuracy is improved, but timing-race problems occur between injection reference and frequency-tracking loop
Solution Approach 1:
The voltage pre-setting stage performs preliminary action by pre-setting the voltage on the capacitive load before the charge-sharing locking phase begins. This preliminary voltage setting ensures that when the oscillator is connected, the phase error correction occurs smoothly without timing-race conflicts between the injection reference and frequency-tracking loop
Solution Approach 2:
The capacitive load serves as an intermediary element between the voltage pre-setting stage and the oscillator. It stores the pre-set voltage and facilitates smooth charge sharing during locking, mediating the interaction between the injection reference and frequency-tracking loop to eliminate timing-race problems
3Adaptability or versatility
If conventional injection locking is used, then integer-N PLL operation is achieved, but fractional-N operation capability is limited
Solution Approach 1:
The system changes the operating parameters of the oscillator by varying the voltage on the capacitive load through the switching network. This allows the oscillator to operate at different frequencies including fractional-N frequencies, achieving fractional-N operation capability without fundamentally changing the PLL architecture
Solution Approach 2:
The charge-sharing locking mechanism serves multiple functions: it enables both integer-N and fractional-N PLL operation, provides phase error correction, and maintains frequency accuracy. This multi-functionality achieves operation mode flexibility without significantly increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed PLL achieves low in-band phase noise, reduced power consumption, and robustness against PVT variations, enabling efficient 5G mmW frequency generation with fractional-N operation, mitigating timing-race problems and improving signal quality.
Implementation Method 1
a shared capacitive load; a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a phase of voltage pre-setting for applying an expectant voltage to the capacitive load
Implementation Method 2
selectively connecting the capacitive load to the oscillator during a phase of charge-sharing locking for correcting a phase error in response to a difference between the expected voltage of the capacitor and the output voltage of the oscillator
Data Source
AI summary
The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.