Charge-Sharing SAR ADC With Segmented Capacitor DAC
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Solution Overview
Problem
Existing analog to digital (ADC) and digital to analog (DAC) converters face challenges in achieving fast conversion speeds, high resolution, and a small footprint while minimizing non-ideal behavior due to charge injection from switches.
Innovation Solution
The proposed solution involves a comparator, a successive approximation register, and a digital to analog converter with a capacitor network that allows for charge sharing between capacitors, using a binary tree structure and dynamic element matching to improve resolution and reduce footprint, and incorporates a differential scheme to enhance noise immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If binary weighted capacitors are used in traditional DAC architecture, then resolution is improved, but footprint area increases significantly
Solution Approach 1:
The capacitor array is segmented into multiple groups (first group, second group, third group) with fewer capacitors in each group. Instead of using all N+1 binary weighted capacitors simultaneously, the invention activates only one group at a time during the conversion process, reducing the total number of capacitors needed while maintaining N-bit resolution capability.
Solution Approach 2:
The invention dynamically switches between different capacitor groups based on the successive approximation process. Control signals enable different groups of capacitors at different times during the conversion sequence, allowing the same physical capacitors to serve multiple resolution levels dynamically rather than requiring all capacitors to be present simultaneously.
2Measurement precision
If more capacitors are added to improve resolution, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The capacitor array is segmented into multiple groups (first group, second group, third group) with fewer capacitors in each group. Instead of using all N+1 binary weighted capacitors simultaneously, the invention activates only one group at a time during the conversion process, reducing the total number of capacitors needed while maintaining N-bit resolution capability.
Solution Approach 2:
Each capacitor group can serve multiple resolution levels through dynamic switching. The same physical capacitors in different groups are used at different stages of the successive approximation process, making them multi-functional rather than dedicated to single resolution levels. This reduces the total capacitor count while achieving the same resolution.
3Measurement precision
If capacitor matching is improved for higher resolution, then measurement precision is improved, but manufacturing precision requirements increase
Solution Approach 1:
The capacitor array is segmented into multiple groups (first group, second group, third group) with fewer capacitors in each group. Instead of using all N+1 binary weighted capacitors simultaneously, the invention activates only one group at a time during the conversion process, reducing the total number of capacitors needed while maintaining N-bit resolution capability.
4Productivity
If conversion speed is increased, then productivity is improved, but non-ideal behavior from charge injection increases
Solution Approach 1:
The invention uses periodic switching between different capacitor groups synchronized with the successive approximation clock cycles. By systematically enabling different groups at different times (first group in first cycle, second group in second cycle, etc.), the charge injection from switches occurs in a controlled periodic manner that can be compensated for, rather than causing random errors.
Solution Approach 2:
The successive approximation register uses feedback from comparator outputs to control which capacitor groups are enabled at each step. This closed-loop control allows the system to adjust the capacitor configuration based on the analog input value, maintaining accuracy while operating at high speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables faster conversions with improved resolution, reduces the footprint of the converters, and minimizes non-ideal behavior, while also providing enhanced noise immunity and accuracy through dynamic element matching and differential signaling.
Implementation Method 1
a digital to analog converter having an input coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, and a third capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first capacitor to the second capacitor and the third capacitor to the second capacitor mutually exclusively to share charge on the first capacitor and charge on the third capacitor with charge on the second capacitor
Data Source
AI summary
In one embodiment, an analog to digital converter includes a comparator having a first input, a second input and an output, the first input being coupled to an analog signal, a successive approximation register having a serial input coupled to the output of the comparator, and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the analog signal, and a digital to analog converter having an input coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, and a third capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first capacitor to the second capacitor and the third capacitor to the second capacitor mutually exclusively to share charge on the first capacitor and charge on the third capacitor with charge on the second capacitor and to generate an analog signal on the second capacitor, the second capacitor being coupled to the second input of the comparator.