Charge-Sharing SRAM Cell for Compact Multi-Bit MAC Operations
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Solution Overview
Problem
Existing memory devices with computing-in-memory architecture face challenges in performing multi-bit operations with high accuracy and linearity, are expensive to manufacture, and occupy large areas due to the use of separate storage elements like capacitors.
Innovation Solution
An SRAM cell configured to perform multiply-accumulate (MAC) operations using charge sharing without a separate storage element like a capacitor, utilizing cross-coupled inverters and transistors to transfer and share charges for multi-bit data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate storage elements such as capacitors are used to perform MAC operations, then the device can perform computing-in-memory operations, but the device occupies a large amount of area and is expensive to manufacture
Solution Approach 1:
The patent merges the storage function and computing function into a single SRAM cell structure. The cross-coupled inverters perform both data storage and MAC computation without requiring separate capacitors, thereby reducing device area while maintaining computing-in-memory capability
Solution Approach 2:
The SRAM cell is designed to perform multiple functions: storing data, performing multiplication operations, and accumulating results. The same cell structure handles both memory storage and arithmetic operations, eliminating the need for dedicated storage elements like capacitors
2Adaptability or versatility
If separate storage elements such as capacitors are used to perform MAC operations, then the device can perform computing-in-memory operations, but the manufacturing cost is high
Solution Approach 1:
The patent combines storage and computing functions in a single SRAM cell, eliminating the need for separate capacitor structures. This simplification reduces manufacturing complexity and cost while maintaining full computing-in-memory functionality
Solution Approach 2:
The patent uses standard SRAM cell structures that are already well-established in semiconductor manufacturing processes, replacing expensive and complex capacitor-based computing elements with conventional, cost-effective transistor-based logic
3Productivity
If current-based MAC operations are performed, then the device can perform computing operations, but the linear characteristic is low (non-linear)
Solution Approach 1:
The patent replaces current-based analog computing with voltage-based digital logic operations using cross-coupled inverters. This substitution provides well-defined voltage levels and thresholds, ensuring linear and predictable MAC operation results
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SRAM cell achieves accurate multi-bit operations with improved integration and reduced energy consumption by eliminating the need for separate storage elements, ensuring linearity in MAC results.
Implementation Method 1
an SRAM cell configured to perform a MAC operation on multi-bit data based on charge sharing
Data Source
AI summary
An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.