Charge Spreading Inhibition Layer for 3D Nonvolatile Memory
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Solution Overview
Problem
As the integration density of semiconductor devices increases, it becomes difficult to scale down and pattern cells in three-dimensional (3D) nonvolatile memory devices due to trapped charges spreading out, leading to data disturbance.
Innovation Solution
Incorporating a charge spreading inhibition layer with negative fixed charges, made of materials like metal oxide, metal nitride, or metal oxynitride, between the channel pattern and interlayer dielectric films, and on the trap layer, to prevent charge spreading, along with a blocking layer configuration to confine charges under the gate patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density of semiconductor devices is increased, then productivity and storage capacity are improved, but trapped charges spread out causing data disturbance and reliability deteriorates
Solution Approach 1:
A charge spreading inhibition layer is introduced as an intermediary between the charge trap layer and the blocking layer/interlayer dielectric. This intermediate layer specifically targets and prevents charge spreading without disrupting the overall memory cell structure, enabling high integration density while maintaining data retention reliability.
Solution Approach 2:
The charge spreading inhibition layer modifies the electrical parameters (charge distribution, electric field) in the critical region between the charge trap and blocking structures. By controlling charge spreading through this layer, the patent enables higher integration density while preventing data disturbance caused by charge migration.
2Reliability
If charge spreading inhibition layer is added to prevent charge spreading, then data retention is improved, but device structure and manufacturing process become more complex
Solution Approach 1:
The charge spreading inhibition layer is applied locally at specific interfaces (between charge trap and blocking layer/interlayer dielectric) rather than throughout the entire device structure. This localized approach provides the necessary charge confinement functionality while minimizing the overall structural complexity and manufacturing burden.
3Reliability
If charge spreading inhibition layer is added to prevent charge spreading, then data retention is improved, but manufacturing process steps increase
Solution Approach 1:
The charge spreading inhibition layer is formed by integrating metal nanoparticles into an existing dielectric material matrix, combining two materials into a single functional layer. This approach adds the charge confinement functionality without requiring completely separate manufacturing processes, as the metal particles can be deposited and embedded within standard dielectric fabrication sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The charge spreading inhibition layer effectively inhibits trapped charges from spreading laterally, enhancing the reliability and data retention of the nonvolatile memory device by maintaining charge confinement under the gate patterns.
Implementation Method 1
The charge spreading inhibition layer may include charges inside or on its surface... including negative fixed charges, preventing trapped chares of the charge trap layers from spreading out
Implementation Method 2
the dielectric layer has higher dielectric constant than a silicon oxide... having a greater dielectric constant than a silicon oxide film
Implementation Method 3
annealing the dielectric layer under an atmosphere of NH3
Data Source
AI summary
A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.