Charge-Steering Phase Discriminator for Low-Jitter Fractional-N ADPLL
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Solution Overview
Problem
Traditional Phase Locked Loops (PLLs) face challenges such as large quantization noise, low phase discrimination gain, high jitter, and narrow locking range, which hinder their ability to generate low-jitter target frequency signals required for 5G/6G communication.
Innovation Solution
The proposed solution involves a Charge-Steering-Sampling Phase Discriminator (CSS-PD), a Digital Loop Filter (DLF), and a Charge-Steering-Sampling All Digital Phase-Locked Loop (CSS-ADPLL) that utilize a Frac-N Capacitive Digital-to-Analog Converter (C-DAC) and a Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) to achieve high phase detection gain, low noise, and wide locking range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional PD is used in PLL, then the structure is simple, but the phase detection gain is low and quantization errors are large
Solution Approach 1:
The patent replaces the traditional analog phase detector with a charge-steering-sampling phase discriminator that operates in the charge domain. This substitution of the detection mechanism enables high phase detection gain while maintaining digital operation, resolving the contradiction between measurement precision and device complexity.
Solution Approach 2:
The invention changes the operating domain from voltage to charge, using charge-steering-sampling to detect phase differences. This parameter change enables the phase detector to achieve high gain without requiring complex analog circuitry, as the charge domain operations can be efficiently implemented with simple switching circuits.
2Adaptability or versatility
If fractional division scheme based on DSM is used, then frequency synthesis is achieved, but large quantization errors occur
Solution Approach 1:
The patent implements periodic fractional frequency division error compensation in the charge domain, using feedback mechanisms to correct quantization errors introduced by fractional division. This feedback approach maintains frequency synthesis versatility while significantly improving frequency precision by eliminating the quantization errors that plague traditional DSM-based systems.
Solution Approach 2:
The invention discards the problematic voltage-domain fractional division approach and recovers precision by implementing error compensation in the charge domain. By discarding the quantization errors at the charge-steering stage and recovering precise frequency control through periodic compensation, the system achieves both versatility and precision.
3Ease of operation
If charge injection locks phase-locked loop is used, then direct phase and frequency calibration is achieved, but reference stray increases and lock position is unclear
Solution Approach 1:
The patent replaces the charge injection locking mechanism with a charge-steering-sampling approach that detects phase differences through sampling rather than direct injection. This substitution maintains the ease of phase and frequency calibration while eliminating the reference stray and lock position ambiguity that characterize charge injection locked systems.
4Extent of automation
If traditional ADPLL is used, then digital phase detection is achieved, but sampling causes periodic interference and large chip area is required
Solution Approach 1:
The patent uses periodic fractional frequency division error compensation instead of continuous sampling to detect phase differences. This periodic action in the charge domain achieves digital phase detection without the periodic interference that plagues traditional ADPLL sampling methods, as the compensation occurs at controlled intervals rather than through continuous sampling of the reference signal.
Solution Approach 2:
The invention extracts the phase detection function from the sampling process itself, using charge-steering-sampling to detect phase differences directly without sampling the reference signal waveform. This extraction eliminates the periodic interference caused by sampling while maintaining digital operation, as the phase information is captured through charge steering rather than signal sampling.
5Device complexity
If bang-bang type PLL is used, then simple control is achieved, but locking range is narrow and lock speed is slow
Solution Approach 1:
The patent implements periodic fractional frequency division error compensation that provides more than just binary correction. By using charge-steering-sampling with multi-level charge states and periodic compensation, the system achieves wide locking range and fast lock speed while maintaining relatively simple control logic, effectively applying partial or excessive correction actions to overcome the limitations of bang-bang control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CSS-ADPLL demonstrates improved phase noise suppression, increased locking speed and range, and reduced chip area and power consumption, effectively addressing the limitations of traditional PLLs.
Implementation Method 1
Frac-N Capacitive Digital-to-Analog Converter (C-DAC)
Implementation Method 2
Successive Approximation Register Analog-to-Digital Converter (SAR-ADC)
Implementation Method 3
two transistors M1 and M2... The two bases of M1 and M2 receive Vref1 and Vref2 respectively
Data Source
AI summary
The present invention discloses a CSS-PD (Charge-Steering-Sampling Phase Discriminator), a DLF (Digital Loop Filter) and a CSS-ADPLL (Charge-Steering-Sampling All Digital Phase-Locked Loop) thereof The CSS-PD includes a Frac-N C-DAC, a CSS, and a SAR-ADC. The CSS-PD has a controlling method including four steps: (1) charge presetting; (2) charge-steering sampling; (3) fractional charge compensating; (4) digitalizing. Wherein when ΔVerr,pn sampled by the CSS included two errors ΔVerr,pn and ΔVerr,frac, ΔVerr,frac had fractional charge compensating by setting part of the capacitors of the Cfrac of the Frac-N C-DAC to a Vref,adc. Vref,adc was satisfied the following formula: ΔVerr,frac=Dfrac·Cunit/(Cfrac+Csar)·Vref,adc. Cunit is for capacitance of Cfrac, Cfrac is also for capacitance of Cfrac, Csar is also for capacitance of Csar of the SAR-ADC, Dfrac is the output signal of the Frac-N C-DAC. A CSS-ADPLL with the CSS-PD can obtain the performance of low jitter, low fractional division spurious and low reference spurious at the same time.