Charge-Steering Multiplexor for High-Speed Low-Power Serialization
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Solution Overview
Problem
Conventional CMOS logic is inefficient for high-speed serializer/deserializer applications, as it does not leverage the potential of charge-steering logic for power savings and speed enhancement.
Innovation Solution
A 2:1 charge-steering multiplexor (MUX) cell is developed, which can be used in a tree fashion to compose a 2N:1 MUX, integrated with conventional CMOS signals at a parallel input and featuring a current-mode driver at the serialized output, utilizing PMOS and NMOS transistors and capacitors to manage clock signals and digital inputs for efficient data serialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional CMOS logic is used in serializer/deserializer applications, then the circuit can operate with standard voltage levels, but power consumption increases and speed is limited
Solution Approach 1:
The patent changes the operating parameters of the logic circuit by implementing charge-steering logic that operates with half the voltage swing of conventional CMOS logic. This parameter change reduces dynamic power consumption (which is proportional to voltage squared) while enabling higher switching speeds due to reduced charge/discharge times for the storage nodes.
Solution Approach 2:
The patent replaces conventional voltage-mode CMOS logic with charge-steering logic that uses charge-based switching mechanisms. This substitution fundamentally changes the operating mechanism from voltage-controlled switching to charge-controlled switching, achieving both lower power consumption and higher speed performance.
2Productivity
If charge-steering logic is implemented, then power savings and speed enhancement are achieved, but integration with conventional CMOS signals becomes complex
Solution Approach 1:
The patent introduces intermediary conversion circuits that translate between conventional CMOS voltage-level signals and charge-steering logic levels. These intermediary circuits act as adapters, allowing seamless integration between standard CMOS interfaces and the optimized charge-steering serialization core, thereby reducing integration complexity.
Solution Approach 2:
The patent divides the serializer into separate functional blocks: conventional CMOS interface stages for signal input and charge-steering logic stages for high-speed processing. This segmentation allows each block to be optimized independently and simplifies the integration interface between different logic families.
3Speed
If voltage swing is reduced to half of conventional CMOS, then higher speeds and power savings are achieved, but signal robustness may be compromised
Solution Approach 1:
The patent changes the signal representation parameter from full-voltage swing to half-voltage swing operating mode. This parameter change achieves higher switching speeds and lower power consumption while maintaining signal integrity through carefully designed charge storage nodes that preserve charge information despite the reduced voltage amplitude.
Solution Approach 2:
The patent uses differential charge-steering where complementary signals are processed in parallel with opposite polarity charge steering. This copying approach with differential signaling enhances signal robustness by providing noise immunity and ensuring that signal integrity is maintained even with reduced voltage swing.
Data Source
AI summary
Disclosed herein is circuitry that extends the charge-steering (CS) logic library with a 2:1 CS-multiplexor (MUX) cell that can be used in a tree fashion to compose a 2N:1 CS-MUX. Also presented is the integration of 2N:1 CS-MUX with conventional CMOS signals at a parallel input, and a current-mode driver at the serialized output. Also presented are a non-return-to-zero (NRZ) to RZ serializing transmitter, a charge-steering multiplexor (CSM) pre-driver, and a CSM transmitter.