Vertically-Spaced Charge Storage Segments for NAND Memory
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Solution Overview
Problem
Conventional NAND memory architectures face data retention issues due to charge migration between memory cells caused by charge-trapping material extending across multiple cells, leading to inaccurate data storage.
Innovation Solution
Incorporating breaks in the charge-trapping material between memory cells and using vertically-stacked charge-storage material segments with dielectric and high-k materials to impede charge migration, along with charge-blocking and tunneling materials to enhance data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge-trapping material is used to store charge in NAND memory cells, then data storage capability is improved, but charge migration between adjacent memory cells occurs causing data retention issues
Solution Approach 1:
The charge trapping layer is divided into discrete vertically-spaced segments rather than being continuous. Each segment is separated by gaps filled with dielectric material, creating isolated charge storage regions that prevent charge migration between adjacent memory cells while maintaining storage capacity within each segment.
Solution Approach 2:
Dielectric material is introduced as an intermediary substance between adjacent charge trapping segments. This dielectric material acts as a barrier that blocks charge migration pathways while allowing each segment to independently store charge, thus resolving the charge migration issue without sacrificing storage capability.
2Ease of manufacture
If continuous charge-trapping material is used across multiple memory cells, then manufacturing simplicity is maintained, but charge isolation between cells deteriorates
Solution Approach 1:
The charge trapping layer is segmented into discrete portions separated by dielectric material. This segmentation can be achieved through selective deposition processes where dielectric material is deposited between charge trapping segments, maintaining manufacturing feasibility while eliminating charge migration pathways.
Solution Approach 2:
Different regions of the memory structure have different material compositions: charge trapping material in active storage regions and dielectric material in isolation regions. This local differentiation enables charge storage where needed while preventing migration in between cells, resolving the contradiction between manufacturing simplicity and charge isolation.
3Reliability
If vertically-stacked charge-storage segments with dielectric materials are implemented, then charge migration is reduced, but device structural complexity increases
Solution Approach 1:
The charge trapping structure transitions from a planar two-dimensional layer to a three-dimensional vertically-stacked configuration. By utilizing the vertical dimension, multiple charge storage segments can be stacked above each other with dielectric isolation, achieving better charge isolation while the regular stacking pattern maintains manufacturing manageability.
Solution Approach 2:
The memory structure employs composite material stacking, alternating between charge trapping material layers and dielectric material layers. This composite structure integrates both functional requirements (charge storage and isolation) into a unified vertical stack, managing complexity through material composition rather than separate components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces charge migration between memory cells, improving data retention and accuracy in NAND memory arrays by using vertically-stacked charge-storage material segments and dielectric materials to isolate and control charge storage.
Implementation Method 1
vertically-stacked charge-storage material segments with dielectric and high-k materials to impede charge migration
Implementation Method 2
vertically-stacked charge-storage material segments with dielectric and high-k materials
Implementation Method 3
charge-storage material segments, gate-dielectric material, channel material, and insulative material
Implementation Method 4
breaks in the charge-trapping material between memory cells and using vertically-stacked charge-storage material segments
Data Source
AI summary
Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.