3D Charge Storage Trench Isolation for Flash Memory Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor flash memory devices face challenges in maintaining sufficient capacitive coupling between the charge storage layer and the control gate due to the downscaling of semiconductor devices, leading to increased programming time and cross-coupling noise between neighboring cells.
Innovation Solution
The implementation involves forming isolation trenches with specific dimensions between charge storage elements to reduce cross-coupling noise while maintaining sufficient gate coupling, achieved by forming a substrate with a first dielectric layer, charge storage elements on opposite sides of the trench, and a control gate layer over a second dielectric layer, where the trench width is optimized to reduce interference and the height of the charge storage elements is suitable for effective coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the cell area is reduced to continue downscaling, then the memory device size is reduced, but the gate coupling between charge storage layer and control gate deteriorates
Solution Approach 1:
The patent transitions from planar 2D gate coupling to 3D vertical gate coupling by forming charge storage elements as vertical stacks extending from the substrate surface through the tunnel oxide and nitride layers to the control gate. This vertical stacking in the third dimension maintains strong capacitive coupling while allowing planar cell area to be reduced for continued device downscaling.
Solution Approach 2:
The patent employs a composite vertical stack structure consisting of multiple materials including silicon substrate, silicon oxide tunnel oxide layer, silicon nitride charge storage layer, and polysilicon control gate. This composite structure integrates different functional materials in the vertical dimension to achieve both reduced planar footprint and maintained gate coupling.
2Ease of manufacture
If conventional shallow trench isolation techniques are used, then fabrication is simplified, but cross-coupling noise between neighboring charge storage elements increases
Solution Approach 1:
The patent introduces an intermediary isolation structure comprising a first dielectric layer formed in isolation trenches between adjacent charge storage elements. This intermediate dielectric material acts as a mediator that electrically isolates neighboring charge storage elements, preventing cross-coupling noise while maintaining the overall fabrication simplicity of trench isolation techniques.
3Loss of time
If the area of floating and control gate electrodes is increased to improve capacitive coupling, then programming time is reduced, but the cell area increases
Solution Approach 1:
The patent moves the charge storage function from a 2D planar floating gate to a 3D vertical stack configuration. The charge storage elements extend vertically through the tunnel oxide and nitride layers to the control gate, creating strong capacitive coupling in the vertical dimension without requiring increased planar area, thus maintaining fast programming times while enabling cell area reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved field oxide mesa widths and reduced cross-coupling noise, enabling efficient and reliable operation of memory devices with enhanced gate coupling properties.
Implementation Method 1
capacitive coupling between the charge storage layer and the control gate
Data Source
AI summary
A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.