Charge-Summing Circuit With Aliased Integration for Wide Dynamic Range
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Solution Overview
Problem
Conventional summing circuits have a limited dynamic range, making it impossible to achieve a total charge corresponding to the sum of several thousands of pF·V, which is essential for applications like terahertz imaging, where a high signal-to-noise ratio is required.
Innovation Solution
A summing circuit design incorporating a capacitor, a switching circuit, an integrator, a hysteresis comparator, and a counter, which alternately increases and decreases an analog signal to alias the sum of charge samples, allowing for a digital representation of the total charge, thereby achieving a dynamic range greater than 106.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional summing circuit with capacitors Ca and Cb is used, then the circuit structure is simple, but the dynamic range is limited by the capacitance ratio Ca/Cb and voltage excursion
Solution Approach 1:
The summing circuit is divided into multiple independent summation stages, each handling a portion of the total charge. The first summing circuit handles charges up to a first threshold, and the second summing circuit handles charges from the first threshold to a second threshold. This segmentation allows each stage to operate within its optimal dynamic range, collectively achieving a much larger overall dynamic range than a single stage could provide.
Solution Approach 2:
The patent extends the dynamic range by adding a temporal dimension through sequential operation of multiple summing circuits. Instead of relying solely on the capacitance ratio in a single circuit, the system uses multiple circuits operating in sequence, where the total charge is accumulated across different time periods and circuit stages, effectively multiplying the available dynamic range.
2Measurement precision
If the capacitance ratio Ca/Cb is increased to expand dynamic range, then the dynamic range improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of requiring one capacitor with an extremely large capacitance ratio, the patent segments the charge summation into multiple stages, each with moderate capacitance ratios. This approach achieves the same overall dynamic range expansion without requiring any single capacitor to have an impractically large ratio, simplifying manufacturing and reducing device complexity.
Solution Approach 2:
The patent introduces intermediate charge storage nodes and control circuits that mediate between the input charges and the final output. These intermediaries allow the system to accumulate charge in manageable increments across multiple stages, avoiding the need for extreme capacitance ratios in any single stage while still achieving the required total dynamic range.
3Measurement precision
If the voltage excursion E is increased to improve dynamic range, then the dynamic range improves, but the power supply voltage requirement increases
Solution Approach 1:
The voltage excursion requirement is segmented across multiple summing circuits operating in sequence. Each circuit operates with a moderate voltage excursion within its own power supply range, and the cumulative effect of multiple stages achieves the total dynamic range needed. This eliminates the need for a single high-voltage power supply.
Solution Approach 2:
The patent employs periodic switching between different summing circuits, with each circuit activated for a specific time period to handle a portion of the charge summation. This periodic operation allows the system to maintain low voltage excursions in each stage while achieving high overall dynamic range through the sequential accumulation of results across multiple periods.
Data Source
AI summary
A summing circuit, including a capacitor, a switching circuit capable of connecting the capacitor between a first node (ana) and a second node (ref), between a third node and the second node in a first connection direction or between the third node and the second node in a second connection direction, an integrator coupled to the third node, a hysteresis comparator coupled to the output of the integrator, and a counter coupled to the output of the hysteresis comparator.