Charge Transfer Reduction Transistor for Memory Electron Injection
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Solution Overview
Problem
The existing single-layer polysilicon type non-volatile memory experiences characteristic variation due to electron injection into gate insulating films during writing operations, which is difficult to mitigate without slowing down the writing process or decreasing read current.
Innovation Solution
Incorporating a charge transfer reduction transistor to reduce electron injection into write and erasure transistors by using a charge transfer reduction gate that receives a voltage similar to the read gate during writing, thereby minimizing electron transfer from the active region to the read and write transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate insulating films are thickened to reduce electron injection, then electron injection is reduced, but writing operation speed decreases and read current decreases
Solution Approach 1:
A charge transfer reduction transistor is introduced as an intermediary component between the bit line contact region and the read/write transistors. This transistor selectively blocks electron injection during writing operations by controlling the potential distribution, thereby reducing harmful electron injection without thickening the gate insulating films and maintaining fast writing speeds
Solution Approach 2:
The invention changes the electrical parameters (voltage potentials) applied to different regions during writing operations. By applying specific voltages to the charge transfer reduction transistor gate and adjusting the potential distribution in the active region, electrons are prevented from being accelerated toward the read/write transistor gate insulating films, thus reducing injection without affecting writing speed
2Object-affected harmful factors
If the voltage applied to the source line is decreased to reduce electron injection, then electron injection is reduced, but writing operation becomes less effective
Solution Approach 1:
Different voltage potentials are applied to different regions locally. The charge transfer reduction transistor is applied with a specific gate voltage that creates a potential barrier only in the region where electron injection to read/write transistors occurs, while allowing the source line voltage to remain sufficiently high for effective writing operations in the memory cell region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces electron injection during writing operations, maintaining efficient writing and reading processes without increasing cell size or slowing down the writing operation, even under high temperature conditions.
Implementation Method 1
a charge transfer reduction transistor (23A) which reduces injection of an electric charge to the write and erasure transistor (21A) and the read transistor (22A)
Implementation Method 2
a part of electrons generated in a part (BL portion) where the contact with the bit line BL in the active region for reading is formed by an electric potential difference between BL and SL are transferred and accelerated in an extending direction of the source line SL
Data Source
AI summary
A semiconductor device includes a semiconductor substrate and a first memory cell disposed on the semiconductor substrate. The first memory cell includes a first write and erasure transistor, a first read transistor, and a first charge transfer reduction transistor. The first write and erasure transistor controls data writing and erasing. The first read transistor controls data reading. The first charge transfer reduction transistor reduces injection of an electric charge to the first write and erasure transistor and the first read transistor.